TDM in MPC8306 query

[will_intelli]

Hello,

I am trying to use the TDM interface in a custom MPC8306-based board running Linux.  I am using the Freescale MPC8306 Linux BSP found here http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC8306&fpsp=1&tab=Design_Tools_Tab which uses Linux 2.6.34.  We are having some issues getting the TDM framer component of the code to transmit packets depending on our TDM clock and TDM sync source.  For one set of clock and sync signals, the TDM interface happily transmits data, for another set, the signals look okay, but we aren't seeing any transmit interrupts and no transmitted data.  If we switch to using baud rate generators instead of external clock and sync, we don't see the same problem.

Has anyone had any experience with the TDM interface in the MPC830x CPUs, and know what would prevent the TDM from transmitting?

Will O'Neill

Software Engineer

IntelliDesign Pty Ltd

http://www.intellidesign.com.au/

[usingbothmuxand]

i am facing a similar problem with MPC8309. i am using TDMB in TSA mode. it is working only when Common RxTx  bit is set. they are not working on independent clocks.

your original problem working on respective clock resolved ?

if yes what needs to be modified?

[will_intelli]

Hi,

Its been a while since I looked at this, but I believe we were using independent clocks for TDMA, and common clocks for TDMB.

[usingbothmuxand]

ok. fine thank you. we mapped to TDMA and it is working fine. seems like we have to use TDMA.  its a serious problem for us as we have to use both TDMs with external inputs only.   NXP should tell us whether they have any such issues with TDMB. i have even checked Errata but nothing mentioned about this limitation.

[alexander_yakov]

Input clock pins are typically multi-function pins. So, if the TDM works properly from internal BRG but does not work from external input clock, than please check how these input clock pins are configured in SICR registers

[will_intelli]

Hi,

I'm pretty certain I have the SICRx registers configured correctly, I have verified against a dump of the registers:

0x114 - 1A 85 55 5E

0x118 - 2B 0A 0B 6F

0x11C - 80 00 00 00

We are actually using TDMA and TDMB, TDMA works okay with an external clock, TDMB only works when running of BRGs.  I've noticed the test code in the BSP is also using BRGs for TDMB, I don't know if this is a coincidence or not though.

Will.

[will_intelli]

We've had some success using shared tx/rx clocks, ie. setting the CRT bit in the SIXMR register., it seems to be working now.

Thanks for your help.