T1023 boot problem

[jaehwansun]

Hi!

I made a commercial board using the T1023NXE7MQA, but when power-on, it does not work. The power-on sequence also works as recommended, and power-on reset configuration and RCW are also normal. (Check with scope)

If this doesn't work, it will not work even if you reset it with the reset switch. However, there are times when it works normally, but it works normally even when reset with the reset switch.

One peculiarity is that when the PRESET is low, the IFC_AD goes low if there is no pull-up register externally (the data sheet says that a pull-up register externally is unnecessary).

Please let me know if there are any causes or solutions.

Thank you

117/5000

[ufedor]

It is needed to doublecheck the processor schematics referring the QorIQ T1023, T1013 Data Sheet, Table 1. Pinout list by bus to ensure that all signals having notes are properly terminated and have correct levels during POR.

[jaehwansun]

T1013 Data Sheet, Table 1. Pinout list has been set as required, but booting fails. After the PORESET goes high, the RCW value stored in the flash is being read properly.

[ufedor]

> One peculiarity is that when the PRESET is low, the IFC_AD goes low

Which exactly IFC_AD signals are low?

How this signals are connected?

[jaehwansun]

All signals go low. 

These signals are connected to nor-flash, FPGA, latch-buffer.
If the IFC_AD signal is high impedance in the FPGA while PRESET is low, these signals will go low. So, while the PRESET is low in the FPGA, some of the IFC_AD signals are made high.

자세히

154/5000

These signals are connected to nor-flash, fpga, latch-buffer.
If the IFC_AD signal is high impedance in the FPGA while PRESET is low, these signals will go low. So, while the PRESET is low in the FPGA, some of the IFC_AD signals are made high.

[ufedor]

Which exactly IFC_AD signals are low and which exactly IFC_AD signals are high when PORESET_B is low?

Which exactly "latch-buffer"?

Which exactly IFC_AD signals are connected to the "latch-buffer"?

[jaehwansun]

The connection is as shown. (Removed FPGA)
What is unusual is the initial waveform and picture of IFC_AD.

[ufedor]

The latch buffer has bus hold which could affect the cfg_rcw_src signals levels.

[jaehwansun]

All signals work normally. (All requirements of T1023 datasheet, Table 1 are also met)
When PORESET goes high, RCW is read from nor-falsh, and when HRESET goes high, the last 8 bytes of RCW are read. After approximately 1.6 ms, ASLEEP goes low. But I can't proceed anymore here. (Sometimes it works normally.) If I go up after systemp up using Trace-32, the program works normally. Please let me know where to look.
Thank you.