SDRAM Interfacing Issue with MPC8270

[toltol]

Dear,

we have interfaced SDRAM (IS42S86400F-7TLI) with processor MPC8270.  Following is the issue that we are facing running SDRAM with MPC8270.
Problem:
If we write 0x12345678 at SDRAM address 0x00000000. The data is correctly written at address 0x00000000. But when we read from 0x2000 same data that we wrote (i.e. 0x12345678) at 0x00000000 will be read from this location. It seems like the 11th bit of column address is not working. When we change the driver to used 10 columns address lines, the data repetition problem is resolved.
Questions:
(1) Kindly tell us how to configure SDRAM with 11 columns in SDRAM machine configuration registers?
(2) Does MPC8270 support SDRAM with 11 columns (A [0-9, 11])? If yes, what should be the proper changes in hardware or software? Should the multiplexing be configured in software or do we have to do external multiplexing?
(3) A similar problem is mentioned in AN2165 (Page 3) “Column Number Limitation for MPC8260 Rev. A and B”. Does the same problem resides in MPC8270 as well? If Yes, how do we resolve this problem (i.e.  using an SDRAM with 11 columns (A [0-9, 11]))?
Following are the software and hardware configurations for our board:
Board Specifications:
(1) 100 MHz Bus frequency
(2) 400 MHz Core frequency
(3) 300 MHz CPM frequency
(4) 512MB SDRAM (8 devices, each 64MB of x8 width arranged in 16M x 8 bits x 4 banks, all connected via CS1)
SDRAM (IS42S86400F-7TLI) Specifications:
(1) 16M x 8 bits x 4 banks    
Note: 8 devices(x8) are interfaced to MPC8270 using 64-bit data bus
(2) 13 Rows (A0 – A12), 11 Columns (A0 – A9, A11)
Driver Sequence:
(1) PSRT: 0x0200     
(2) MPTPR: 0xF9          Note: Refresh interval will be 7.5uSec
Interval = (249+1) x (2+1)/100000000 = 7.5uSec //8192 rows having 64ms refresh time yields 7.8uSec
(3) OR0: 0xE0002700
SDAM     = 0b111100000000
LSDAM    = 0b00000
BPD        =0b01
ROWST    =0b0011
NUMR    =0b100
PMSEL    =0b0
IBID        =0b0
(4) BR0: 0x00000041
BA        =0b00000000000000000
PS        =0b00
DECC        =0b00
WP        =0b0
MS        =0b010
EMEMC    =0b0
ATOM        =0b00
DR        =0b0
V        =0b1
(5) PSDMR: 0xC536B673
PBI        =0b1
RFEN        =0b1
OP        =0b000
SDAM        =0b101
BSMA        =0b001
SDA10    =0b101
RFRC        =0b101
PRETOACT    =0b011
ACTTORW    =0b011
BL        =0b0
LDOTOPRE    =0b01
WRC        =0b11
EAMUX    =0b0
BUFCMD    =0b0
CL        =0b11        

Hardware Connections:
MPC8270        SDRAM
A28            A0
A27            A1
A26            A2
A25            A3
A24            A4
A23            A5
A22            A6
A21            A7
A20            A8
A19            A9
PSDA10            A10
A17            A11
A16            A12
A15            BA0
A14            BA1

[r8070z]

Have a great day,

The MPC8270 can support 11-bit column address in the same way as it shown in the app. note AN2165 in single-MPC82xx mode. It requires for 2->1 external multiplex for proper generation of SDRAM A11 signal.  You should correct hardware connection (A17 <-> SDRAM_A11).  Your case directly corresponds to the AN2165 example (64-bit data bus, 4 internal banks, 13 row address lines, and 11 column address line) in section 4.3 “1-Gbyte SDRAM Memory Module”. Please see details in that section. 

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[toltol]

Dear Serguei

The AN2165 example in Sec 4.3, Fig 4.3 shows A17, A18 and PSDAMUX being multiplexed to A11.

Do we follow exactly the same hardware configuration or do we ONLY need to mux A17 and A18 to A11?