MPC8640D PCIe Eratta: "Silent" Root Complex, End Point or Both

[stevebumbalough]

Ref: Doc MPC8641DCE, Rev 1, dtd 07/2009.

Page 120, PEX #18.

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The eratta is "silent" with respect to which PCIe ports it is applicable to, whether Root Complex, EndPoint, or both.

Does the eratta apply to Root Complex Only? or, said a different way, does it apply to only the ports that the processor is "master" of (ie: The processor asserts reset on only the RC ports)

Because, if it also applies to End Points, then how does the End Point notify (signal) the bus master that the Endpoint is about to assert a reset on it's end?

In our system, interrupts / exceptions are not enabled during this initialization time, therefore an inbound interrupt signalling event of a port "going down", is not signalled to the processor.

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[r8070z]

Have a great day,

The PEX 18 erratum is related to the PCIe link training and applies to both - RC and EP. So they do not specify if PCIe controller is in RC or EP mode in the Description section. But latter in the Work around section they say directly: “the PCI Express controller may be reset by performing the following procedure in the boot code for both root complex and endpoint applications”

The RC PCIe controller hardware recognizes if link training in-between EP and RC failed. Processor which controls PCIe controller in the EP mode restores this controller without assistance of the RC in the ways suggested in the Work around section.

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