Hello all,
I'm designing my board using MPC8548E Processor SoC interfacing with four discrete DDR2 chips(MT47H64M16NF-25E) to have x64 data bus. MPC8548E provides 6 MCK+/- DDR2 Clock pins. I have basic query which are helpful for me to proceed in design. Please help me out.
1. Six DDR2 Clock differential pair outputs are provided by MPC8548E. Are all clocks active at a time? So, that I can connect my DDR2 chips to any of the 4 clock output among the 6 outputs
2. I'm interfacing 4 DDR2 chips with MPC8548E. Should I share a single clock with all the DDR2 chips?
3. In my board layout, I'm placing two DDR chips on top layer and two on bottom layer. Can I have two clocks such that one clock will be used for two DDR chips on top and another clock will be used for two more DDR chips on bottom
4. Is there any link between Clock and Data pins. For example, 1st DDR chip will connect to DQ0-DQ15 lines and 2nd DDR Chip will connect to DQ16-DQ31 lines. In this case, should I use connect MCK0+/- to 1st DDR chip and MCK1+/- to 2nd DDR chip respectively ? or Can I use any of the clock out of 6 available clock outputs.
5. Can I go with the implementation of having a dedicated clock to each discrete DDR chip i.e., using 4 clock outputs for 4 DDR2 chips.
