MPC8548 eTSEC 104 erratum

[robertbracero]

For the MPC8548 eTSEC 104 erratum, is it possible to get clarification on what is considered a low platform to Rx_clk ratio and slow memory system?

The SBC that we are supporting has a 400 MHz platform clock, a DDR2 frequency of 200 MHz, and the eTSEC is in MII mode running at a max speed of 100 Mbps. Is it safe to assume that eTSEC 104 is not applicable in this case?

[bpe · Accepted solution]

There is no simple criteria to determine if this erratum hits your
system or not. The key is the memory subsystem load which depends
on both the clock ratio and activity of other masters. Basically,
this erratum is very unlikely to hit a 100 Mbps link, but if you
want to be completely sure, stress load (means, all possible DMA +
core/cache active) tests are advised.

Have a great day,
Platon

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