MPC8377: PCIe inbound addressing more restrictive than PCI32 ?

[sylvainbourré]

Hello

We developed several designs based on MPC8377VRAGD with 2-GByte SDRAM,  connected to an FPGA through PCI32 (the FPGA has no local SDRAM attached).

The FPGA fills up the SDRAM attached to the MPC with acquisition data (1768MB of data from physical addr.  0x1000_0000). Everything works fine.

We decided to move from PCI32 to PCIe for a new design (MPC8377 is RC).

The FPGA,  PCIe initiator, is not able to fill up the whole SDRAM with data: posted TLP writes silently fail when destination addr is >= 0x3FFF_F000. TLP reads from the same memory locations fail with completion errors.

I started to investigate in low level u-boot init code and MPC8379ERM and discovered the following:

-    PCI inbound window attributes registers (PIWARn) allow to specify up to 2-Gbyte window size

-    PCI Express RC inbound window attributes registers (PEX_RCIWAR0 –PEX_RCIWAR3) allow to specify up to 256-Mbyte window size

So I have the feeling that our FPGA won’t be able write more than 1GB (4x256MB) into the MPC’s SDRAM.

Can you, please, confirm or infirm this?

If so, any idea for a workaround (dynamic RCIWAR reconfiguration for instance) ?

Thank you in advance for any comment/advice.

[r8070z]

Have a great day,
 

Yes the MP83xx PCI Express RC inbound window attributes registers (PEX_RCIWAR0 –PEX_RCIWAR3) allow to specify up to 256-Mbyte window size.

May be your FPGA can be PCIe Root Complex? The MPC8377 as EP can have 2GB inbound window.

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[sylvainbourré]

Serguei,

Thank you but using the MPC8377 as EP is not an option.

One more detail: the FPGA fills up the SDRAM in a linear way and informs the software of the progress (it triggers an HW interrupt then the MPC reads an FPGA register containing the future write address).

What about reconfiguring inbound windows dynamically? I know it seems tricky but can it be done is a safe way?

TIA

[r8070z]

I think it can be done if we will use 2 inbound windows. The first window is in use while the second is reconfigured and vice versa. Because the FPGA is only one which uses the windows you can controls that there is no any access to particular window when you can disable it, change the base address and re-enable.

[sylvainbourré]

Thank you Serguei.

FYI, I implemented it (using all the 4 inbound windows to be less sensitive to interrupt latency as I can't tell my FPGA to slow down writing) and it works !

Hope this is reliable...

Have a good week end.

[r8070z]

It is nice! Thank you for information about solution.