Have a great day,
I do not see your BRGCx[EXTC], BRGCx [DIV16], BRGCx[CD] and GUMR_L[TDCR] settings. . Maximum the BRGCLK to baud rate divider is 16*4096*32. For BRGCLK = 83.33MHz please check that BRGCx[EXTC]=0, BRGCx [DIV16]=1, BRGCx[CD]=270 and GUMR_L[TDCR]=0b10 (16x clock mode - normally chosen for UART). If it is possible please check also BRG output clock frequency on the corresponding BRGO pin for these settings.
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