MPC8260 UPM and SRAM interfacing

[supriyoganguly]

We have been using MPC8260. We have connected UPM with SRAM 1MB through FPGA. Port size = 16bit. From processor address lines, data lines, CS, BS, bctl0 and UPMWAIT is connected to FPGA. PSDVAL, TA and TEA are connected to pull ups. We found that after assertion(low) and de-assertion(high) of UPMWAIT, sometimes CS is still asserted. What is the possible reason and solution to this issue?@

[r8070z]

Have a great day,

I assume you operates in the single PQII bus mode (when connects external devices by using only the memory controller.

When the LAST bit is read in a RAM word, the current UPM pattern terminates. On the next cycle all the UPM signals should be negated (driven to logic ‘1’). However this negation will not occur if there is next a back-to-back UPM request pending. In this case the signals value on the cycle following the LAST bit, will be taken from the first line of the pending UPM routine.

  So I can imagine that while UPMWAIT freeze the current access the next request for UPM access may come and CS will be kept asserted for the next access.

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