I am working on mpc8358 processor, I am using DDR SDRAM memory, I need some reference documents for configuring the controller. I have an AN3399 document but it is referring to DDR2. please provide me DDR1 ref doc.
Mutual correspondence of the MDQ and DQ signals is irrelevant for the DDR and DDR2 SDRAM if data lane structure is preserved - refer to the MPC8360E PowerQUICC II Pro Integrated Communications Processor Family Reference Manual.
