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- MPC8541 Power Management Specific FAQs
MPC8541 Power Management Specific FAQs
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MPC8541 Power Management Specific FAQs
MPC8541 Power Management Specific FAQs
I would like to know if output signals of blocks which are not clocked during sleep mode are driven or not. For example, are eTSEC2 RGMII signals driven during sleep mode?
Yes, they would be driven but there would be no activity on them. Please note that this is for "sleep" mode NOT "deep sleep"
MPC8541 supports “Wake on LAN” from the Deep Sleep. If TSEC operates via SGMII it needs for SVDD,XVDD, SVDD2,VDD2, SDAVDD and SDAVDD2 (SGMII power). All these powers are switchable in the Deep Sleep. Can we leave these rails powered in the Deep Sleep and expect that the MPC8541 will support “Wake on LAN” via SGMII?
Serdes is powered down during deep sleep, so Wake up on LAN is not supported for Deep Sleep in SGMII mode. Wake on LAN is supported for RGMII. Please note only eTSEC1 supports this feature. (Assuming eSTEC1 and eTSEC2 as the nomenclature)
Are there any pull-downs for signals POWER_EN and ASLEEP on the MPC8541 board? Is BVDD switched off using POWER_EN?
LOE has pull down via 4.7k ohms resistor as POR config. LWE has neither pull-up nor pull-down. Yes, BVdd is switched off using POWER_EN.
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