I would like to start off with the fact that I am still waiting on receiving access to AN5238 and FS6500-FS4500SMUG. Maybe the answer to my questions is listed in there, but given the fact that I've already been waiting a few weeks, I'd like to ask my questions here.
The FS6500-FS4500 datasheet (Publicly available, thankfully) lists that VAUX requires an external PNP as it has no internal current handling capabilities. The max rating for IAUX is 400 mA. Current limitation kicks in between 400 and 800 mA. The datasheet in no way explains how this current detection is implemented, leaving me with the following questions:
So in short and in general: What does the internal circuitry of the VAUX function block look like? How does it work?
Hi G.w. Sun,
Thank you for your response. Are you talking about the internal NPN of the VAUX LDO inside the FS65&FS45? If so, does that mean the limitation for IAUX listed in the datasheet is based on assumptions about a certain range of hFE for the external PNP?
What limits exist for the hFE of the external PNP? This is listed nowhere in the datasheet, and I am missing any other rationale for the value of 400 mA that is listed in the datasheet.
According to the datasheet, the external transistor should be PNP, not NPN. That's what got me confused.
For VCCA, the datasheet lists 100 < hFE < 450. For VAUX no limits are listed. Should I assume the same limits apply, and the datasheet is lacking?
Thank you. I've now also received access to AN5238 and this confirms that hFE for PNP should be between 100 and 450. I still have a few questions about how this influences the current limitation range, but I believe this platform is not the right place to ask, so I've opened a case through NXP support.
Thanks for your time,