Hello,
I have an issue in a prototype using the TEA2017AAT/2 where the PFC stage seems to limit the current during startup for approximately 900ms after the input is applied:
CH1: PFC Vout
CH2: LLC Vout
CH3: Vin
CH4: Iin
120Vin, 100% power:
Startup is interrupted as the PFC output voltage does not regulate properly until around 1s.
220Vin, 100% power:
The PFC stage is able to regulate here because the current draw is lower. However, the change in behaviour can still be seen after 900ms.
The peak of the input current increases after approximately 900ms from when the input is applied, and then the converter behaves as normal.
Left of the cursor is the current is flattened, right is normal.
The controller has been programmed to operate in DCM/QR mode.
Is there anything inside the TEA2017 which would match this timing? Why is the PFC stage limiting the current?
Thanks,
Connor
Hi guoweisun,
I disabled the LLC stage and supplied the TEA2017 SUPIC pin through a diode with 20V due to the absence of switching on the auxiliary winding.
I tried to match the same output power as when the LLC stage was running.
220Vin, 100% power:
The flattening of the input current is still happening, and the timing is the same.
One thing to note is that the consistent timing of ~900ms is from when the input voltage is applied, not when the PFC stage starts. Due to the 20V on SUPIC the PFC stage starts as soon as input is applied, but in the test with the LLC stage running the SUPIC pin needs to charge before the PFC stage starts, yet the timing of this anomaly is the same.
Thanks,
Connor
