S32K358 + FS26: FS0B not released after initialization / Debug voltage issue

[thorben_kamp]

we are currently working with the S32K358 and the FS26 and are facing some issues during the initialization of the FS26 SBC.

Our setup:

• RTD AUTOSAR 4.7
• SBC Software Version 5.0.0

Debug voltage issue

While debugging with our tracer, we noticed something unusual:
VDBG_VOLT_S is reported as 1, even though the measured debug voltage is around 0 V.

The picture shows the result of the Request. 

Debug Pin Connected

FS0B not released after initialization

After calling the initialization functions:

Sbc_fs26_Init(&Sbc_fs26_xConfig);
Sbc_fs26_InitDevice();

the fault line (FS0B) is not released as expected. When analyzing the code, we noticed that in the function Sbc_fs26_FsxbRelease, the faults should be cleared via Sbc_fs26_ClearFaultErrorCounter(). However, this does not happen in our case. In the Attachements there is the clearFaultCounter routine. The last Messge shows that the counter is not decreased. Even after Sbc_fs26_TimeWaitClearFault() the fault stays unchanged.

As a workaround, we currently:

1. Call Sbc_fs26_DisableWatchdog() before releasing FS0B
2. Then reconfigure the watchdog window to 128 ms afterwards

We tried also to exit the debug mode similar to Sbc_fs26_ExitDebugMode without success.

Questions:

• Are there any Analyzer for the FS26 to debug the trace?
• Any experienced with a similar issue with FS0B not being released after initialization? 
• Why would Sbc_fs26_ClearFaultErrorCounter() only work when the watchdog is disabled?
• Why is the VDBG_VOLT_S not 0 ?

[RafaR]

Hello thorben_kamp

Good Day!

1.- There is no FS26‑specific analyzer, but you can use FS26 registers (FS_STATES, FS_DIAG_SFATY, etc.) as the only “internal visibility” the chip provides.

Debug mode entry can be verified with the bit DBG_MODE in FS_STATES register (latched information). DBG_MODE bit must be equal to ‘0’ in application mode.

2.-  yes

When FAULT_DFS_EN_OTP = 1 the device enters the Deep Fail Safe state upon detection of an RSTB or FS0B fault, regardless of the actual states of the RSTB or FS0B pins

En la version complete de la datasheet (que se encuentra en secure files) puedes encontrar todos los registros que se ven afectados o que afectan a FS0B

3.-

A watchdog refresh must occur only in the open window. Refreshing too early or too late creates a new safety event, incrementing the fault counter.

This prevents the error counter from decreasing, therefore blocking FS0B release.

4.-

the FS26 enters DEBUG mode only if the debug pin voltage VDBG (2.5–6 V) is applied before VSUP.

If the FS26 thinks it entered DEBUG mode, the internal debug‑voltage status bit remains active even when the external pin later falls to 0 V.

I hope this information has helped you, please let me know if you need help with anything else.

Have a great day and best of luck.

[thorben_kamp]

Thanks for your reply.
to 2:
Thanks, we will check the register values
to 3:
Is there a recommended configuration in MCAL so that the fault line is released after initialization, without a workaround?

[thorben_kamp]

here is the picture of the trace  again: