PMIC PCA9450CHNY Not Work

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PMIC PCA9450CHNY Not Work

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Justinou
Contributor I

Hi Sir,

We design PMIC PCA9450CHNY in our I.MX8M plus board.
When  VSYS=5V without loading (0A), we measured LX5 pin and found that spike max upto 7.133V. (please refers to screenshot)

Will this spike (7.133V) cause PMIC IC damage? 
That's a reason why spec mentioned that LX5 pin voltage can't over INB45(5V)+0.5V= 5.5V?

Thanks

spike max upto 7.133V on LX5 pin_PCA9450CHNY.jpg

 

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guoweisun
NXP TechSupport
NXP TechSupport

Hi 

This test value just only can be used as a reference because it shouldn't  be represented as the real value,  during test also there is the test error included.

According the spec if above 5.5V the PMIC had already damaged.

Hope you can understand!

 

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4,423 Views
Justinou
Contributor I

Hi Guowesun

Thanks for your replied. You mentioned over 5.5V, PMIC IC already damaged?

After double check on PCA9450 spec page 61

https://www.nxp.com/docs/en/data-sheet/PCA9450.pdf

Limiting values on LX5 should be upto 6.5V?
If LX5 over 6.5V, PMIC IC will damage.
Does my understanding correct?

Thanks
Justin

 

Page 61 Limiting values_PCA9450CHNY.jpg

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guoweisun
NXP TechSupport
NXP TechSupport

Sorry that give your typo,the limited value should be up to 6.5V.

Perhaps you didn't understand my answer:

That customer test waveform can't represent the real status of LX pins because the test already decouple the error (probe R/C/L parasitic parameter )so it seems much larger than actual value.

I also believe that's very difficult for customer to test the real value of IC's LX pin.

 

 

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4,409 Views
Justinou
Contributor I

Hi Guowesun, 

Thanks for your repied.  We would like to double check more informartion on PMIC IC itself.

Would you explain what is the meaning of the footnote shown below?
What is the breakdown voltage V(BR)DSS of the internal MOSFETs of the PCA9450? Is it allowed that they enter Avalanche mode if the voltage spike exceeds the breakdown voltage?

Page 61 footnote

[1] LX voltage overshoot and undershoot above or below the absolute maximum rating during power transistor switching period is normal and guaranteed by
design as it is already checked in design phase in the point of device safe operating area (SOA) and lifetime.

 

Page 61 Limiting values footnote 1 LX voltage_PCA9450CHNY.jpg

Thnaks

 

 

 

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4,399 Views
guoweisun
NXP TechSupport
NXP TechSupport

This topic is somewhat sensitive and may not be appropriate to post in a public community. I request that you create a ticket and we will respond privately. When creating the ticket, please specify it is for "this topic" to Guowei Sun.

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