PF3001 Power/Pins function

[shashank1]

Hi All,

I have few confusions in the schematics and functioning of few pins. 

1. I am using 5V from USB to power the IC. So, should I connect the net from VIN (after bypass capacitors & PMOS pass FET) to power ON all the switchers & LDO? (4.5V to all the LDOs & switchers- Typical power map in page 26 of datasheet made me to think of this). 

2. I am not using VSNVS, LICELL pins. Can I connect to Vin with bypass capacitors & leave it as it is?

3. Can VLDO34 pin(pin21) be connected to VIN if am using VPWR mode. (voltage greater than 4.5V-in the reference design its connected from SW2). Also what about VLDO2IN.? 

4. Input to switching regulator tells that to use 10uF & 0.1uF in page number 32.
But in functional description, it is told 4.7uF & 0.1uF. Which one should I follow?

5. Is the input voltage is called the main band gap voltage?

Attached are the datasheet & reference schematics. 

Please help

Thank you.

[shashank1]

Hi there,

I have a doubt in the functioning of PWRON pin. 

I have given 3.3V to PWRON (pin 48), from the 1.8V to 3.3V converter. Here 1.8V comes from one of the switcher of PMIC and goes to a processor, from the processor I am enabling the GPIO to supply 1.8V, which is fed to level converter and hence it supplies the 3.3V to PWRON. 

So, now the question is, when I feed the input voltage from VPWR, PMIC will be ON right? Or it depends on only PWRON pin. My processor is not ON initially to supply 3.3V to PWRON pin.

Thank you.

[reyes]

Hi,

Yes, VLDO3 and VLDO4 can be programmed individually using the bits VLDO3[3:0] from VLDO3 control register (VLDO3CTL) 0x70 and VLDO4[3:0] VLDO4 control register (VLDO4CTL) 0x71 respectively. Check Table 48 (Table 48. VLDO3, VLDO4 output voltage configuration), on page 38 of the datasheet.

Check sections 6.6.5.3.33 and 6.6.5.34 on page 73 of the datasheet.

Voltage levels of PF3001 set by default depends on the Pre-programmed OTP configuration (A1, A2, … A7), these are shown on Table 32 of the datasheet: https://www.nxp.com/docs/en/data-sheet/PF3001.pdf

For customized PMIC, I recommend you to contact your NXP sales representative or your NXP Authorized distributor and depending on the opportunity, NXP fabric or distributors can make a custom part number with your specific power up requirements.

Regards,

Jose

NXP Semiconductors

[shashank1]

Hi,

When the input is 5V, what is the voltage available after the PMOS? Is it 4.8? or 4.5? In the datasheet its mentioned 4.5. But in the reference schematic its 4.8V, which is true? And what is the significance of PMOS? 

[shashank1]

Hi,

1. What is the current consumption of the VDDIO pin as individual for 1.8V? How do I find it? 

2. What is the current consumption of PMOS used.?

3. Is the Output of the PMOS is 4.5V or 4.8V? In the reference design why it is 4.8V?  

[shashank1]

Hi,

Can you help in reviewing the PF3001 schematic? 

[reyes]

Hi,

For schematic review, please enter a new ticket in the following link:  Support | NXP 

Regards,

Jose

[shashank1]

Yes. I will. Thank you. 

[shashank1]

Thank you.

[reyes]

Hi,

[A1]

Correct, connect VIN pin to drain of an external PFET when VPWR LDO is used for systems with input voltage > 4.5 V as in figure 7 of the datasheet.

The input pins of the switching regulators should always be connected to the VIN net.

For the LDOs, depends on each regulator:

For VLDO1IN, the maximum operating input voltage for the LDOs is 4.55 V when VPWR LDO is used.

For VLDO2IN, max is 3.4V.

For VLDO34IN, max is 3.6V.

For VIN2, max is 4.8V

[A2]

If unused, connect VSNVS pin with a bypass capacitor of 0.47 μF to ground, and bypass LICELL pin with 0.1 μF.

[A3]

For VLDO2IN, max is 3.4V.

For VLDO34IN, max is 3.6V.

I would not recommend to connect these pins to VIN

[A4]

You can use 4.7uF and 0.1uF. We have been used 4.7uF and 0.1uF for our designs and works well.

[A5]

No, Main bandgap reference voltage is called VCOREREF.

Regards,

Jose

NXP Semiconductors

[shashank1]

Hi, adding to that,

I have few more confusion on the following, It would be very helpful.

1. Reset pin(pin-3): Should it be connected to Master's(or controller's) reset pin? or any GPIO. (I think its Master's Reset pin) And have given a pull-up of 1.8V. Is that correct?

2. INTB pin(pin-1): Have connected to 1.8V GPIO & have given a pull-up of 1.8V.

3. SD-VSEL (pin-2): Have connected a 1.8V GPIO.

4. PWR-ON (pin-48)- Have connected a 1.8V GPIO. 

Thank you.

[reyes]

Hi,

[A1] RESETBMCU (pin 3):

This pin is an Open drain, active low, reset output to processor.

Connect it to Master’s RESET pin (typically called POR pin), and connect a 100k pull-up resistor to VDDIO if the processor’s POR pin does not include an internal pull-up.

[A2] INTB (pin 1):

This pin is an Open drain, active low, interrupt signal to processor. Connect a 100k pull-up resistor to VDDIO (1.8V GPIO is correct) if the processor’s GPIO does not include an internal pull-up.

[A3] SD-VSEL (pin 2):

This is an Input pin from processor to select VCC_SD regulator voltage. The VCC_SD voltage depends on the state of the SD_VSEL pin.

• SD_VSEL=0 (voltage between 0.0V and VDDIO*0.2V), VCC_SD = 2.85 V to 3.3 V
• SD_VSEL= 1 (voltage between 0.8V*VDDIO and 3.6V), VCC_SD = 1.8 V to 1.85 V

When SD_VSEL = HIGH, the VCC_SD regulator operates in the lower output voltage range. The SD_VSEL input buffer is powered by the VDDIO supply.

Typically, this pin is connected to a processor SD_DATA pin directly, which is in the range of VDDIO voltage levels (1.8V GPIO is correct).

[A4] PWR-ON (pin 48):

This pin is the Power ON/OFF input from processor.

Voltage levels on this pins are dependent on the VSNVS voltage levels:

LOW when voltage is between 0.0V and VSNVS*0.2V

And HIGH when voltage is between 0.8V*VSNVS and 3.6V.

Regards,

Jose

NXP Semiconductors

[shashank1]

Hi, 

Does this mean , [A4] PWR-ON (pin 48) it can be controlled from GPIO pin of voltage 1.8V?  Is that correct? 

[reyes]

Hi,

No, VSNVS is 3.0V, so, PWRON pin LOW level goes from 0.0V to 0.6V, and HIGH level goes from 2.4V to 3.6V.

1.8V would not be recognized as a HIGH level.

Regards,

Jose

NXP Semiconductors

[shashank1]

Hi

Can VLDO3 & VLDO4 be programmed individually?
And can we ask to pre-program PF3001 for the required voltages (of-course within the specified range of switcher/LDO, like the customised) from NXP?

Or voltage levels of PF3001 are set by default as shown in the datasheet?  

[shashank1]

Thank you. 

[shashank1]

Thank you. 

[shashank1]

Thank you so much for the clarification.