Migration from TEA1795T to TEA2095T

[AvnetLLC]

Dear NXP,

While migration two questions.

1. On the attached do we need RDRNSENS resistor on TEA2095T?

2. If i get push-pull circuit on gate signal with TEA2095T then does INTERLOCK function get impact? 

Thanks!

Saint

[AvnetLLC]

Hi Tomas,

Your feedback is very valuable as for me. Thanks a lot!

BTW, SR FET Drain-source voltage exceeds 60V when we connect buck-USB PD evk board made by INJOINIC. Our EVK FET Vds is 60V grade so we disconnect buck-USB PD evk then Vds is 51V.

Looks there is no mis-probing. How is your idea on this phenomenon?

BR/Saint

[TomasVaverka]

Dear Saint,

I am sorry, I do not have an answer for this question as I am not an expert in the USB PD application and the USB PD EVK board from INJOINIC.

Best regards,

Tomas

[AvnetLLC]

Hi Tomas,

Don't mention it. 

Once i get the reason will share you first.

BR/Saint

[TomasVaverka · Accepted solution]

Dear Saint,

1. Resistors in series with the drain are not necessary and not recommend when using the TEA2095. The TEA2095 has different internal IC circuitry connected to the DSA and DSB pins. Adding resistors can even degrade the regulation of the adaptive gate drive due to a voltage offset because of small currents flowing into the DSA and DSB pins.

2. The interlock delay time function has a typical value of 200ns. The push / pull circuits will add a switch-on and switch-off delay time to both outputs. When the switch-on delay time and switch-off delay time of the push / pull circuit are the same, then it will not have an effect on the delay / none-overlap time. If the switch-off time of the push / pull circuit is longer than the switch-on delay time, then the resulting  delay / none-overlap time will be shorter. Measuring the timing with an oscilloscope can be used to find what exactly the effect of the push / pull circuit is on the delay time.

Best regards,

Tomas