MMPF0100F0AZES Assembly Failure in Production Stage

[pratikpanchal]

Hello Team,

We have used MMPF0100F0AZES PMIC in our design.

Currently we are on production phase and we are seeing the 30% failure due to issue in PMIC.

We are unable to get any voltage rails from the PMIC. We checked that input voltage is reaching to the PMIC's input pin.

We checked the quality of assembly and X-ray & both looks good to us.

Let us know other important parameter that we need to look for this kind of failure.

Here is the schematic file is attached for your reference.

[pratikpanchal]

Hello Devid,

Kindly find the response.

NXP: Based on the VDDOTP pin, are you using the fuse mode? The OTP configuration is enabled by connecting VDDOTP to GND.

Pratik: Yes, We are using the fuse configurations.

David: Are you connecting the expose pad to the inner and external ground planes through multiple vias to allow effective thermal dissipation?

Pratik: We have provided expose pad to the inner ground planes through vias.

David:

Below, you may find some minor recommendations from your schematics:

SDWNB pin - Pull-up via 68 kΩ.

RESETBMCU pin - Pull-up via 68 kΩ.

SWxAIN pins – Connect to VIN and bypass with 0.1 μF + 4.7 μF to ground.

VGEN1,3,6 pins - Bypass with 2.2 μF to ground.

SWBSTIN pin - Connect to VIN and bypass with 0.1 μF + 10 μF to ground

Pratik: Provided changes are schematic changes but without these changes 60% DUT boards are working fine in the production batch. Let me know how this changes will able to help me out.

Request you to provide the meaning of below  sr no# which we found printed on the IC,

MMPF0100

F0AZES

XACDPH

[diazmarin09]

Hello Pratik,

I am pleased to contact you again.

Could you please review the following conditions before going forward in the issue?

1. On a failed board, could you please make sure the VGENxFAULTI interrupt is not generated?

If a short-circuit condition is detected, the LDO is disabled by resetting its VGENxEN bit, while at the same time, an interrupt VGENxFAULTI is generated to flag the fault to the system processor. The VGENxFAULTI interrupt is maskable through the VGENxFAULTM mask bit. Please review the chapter 6.4.6.2 from datasheet for further information.

2. In the event of excessive power dissipation, thermal protection circuitry shuts down the PF0100. This thermal protection acts above the thermal protection threshold listed in Table 7 from datasheet. To avoid any unwanted power downs resulting from internal noise, the protection is debounced for 8.0 ms. This protection should be considered as a fail-safe mechanism and therefore the system should be configured so protection is not tripped under normal conditions.

3. Is the SDWNB pin asserted?

SDWNB is an open drain, active low output notifying the processor of an imminent PMIC shut down. It is asserted low for one 32 kHz clock cycle before powering down and is then de-asserted in the OFF state.

Finally, based on the information provided, the top marking of your device seems correct. It refers to the assembly split lot, wafer lot and date code. Unfortunately I am not able to provide further information as it is internal and confidential.

I hope this information helps.

Regards,

David

[diazmarin09]

Hello Pratik,

I hope all is great with you.

Based on the VDDOTP pin, are you using the fuse mode? The OTP configuration is enabled by connecting VDDOTP to GND.

Are you connecting the expose pad to the inner and external ground planes through multiple vias to allow effective thermal dissipation?

Below, you may find some minor recommendations from your schematics:

SDWNB pin - Pull-up via 68 kΩ.

RESETBMCU pin - Pull-up via 68 kΩ.

SWxAIN pins – Connect to VIN and bypass with 0.1 μF + 4.7 μF to ground.

VGEN1,3,6 pins - Bypass with 2.2 μF to ground.

SWBSTIN pin - Connect to VIN and bypass with 0.1 μF + 10 μF to ground

Regards,

David