MC34PF3001A7EP

[shwethanarayan]

Hi,

Please find the attachment. We are using IMX6 Ultralite processor for one of our project. We have a small query in PMIC PF3001.

1. What is the SW1_SEQ, SW2_SEQ and so on?

2. If it is a sequence, then why in A7 series it is mentioned as 3 everywhere.for SW1_SEQ, SW2_SEQ and so on.

3. Do you have EVK with PMIC PF3001 for IMX6 Ultralite?

Please let me know the answers for the above queries.

Regards

Shwetha

[reyes]

Hi,

[A1] The SW1_SEQ, SW2_SEQ and so on depends on the OTP configuration, for example, for the A7 (the one you highlighted), all the enabled regulators starts at sequence ‘3’, but the V33 regulator which starts at sequence ‘2’.

[A2] The SEQ_CLK_SPEED is set to 2.0ms, which means that every regulator set to SEQ ‘3’, will turn-on after 3 times SEQ_CLK_SPEED (2.0ms), so, 6ms after power-on the device. Same with the regulators set to SEQ ‘2’, these will turn-on 4ms after power-on the device.

[A3] Unfortunately no, the is no EVK with PMIC PF3001 for IMX6 Ultralite, there is a reference design, however, it is not publicly available, you need to request it with your NXP Authorized Distributor by signing an NDA.

Regards,

Jose