FS4500 SBC: SPI error for the first command

[VN]

Hi,

For the first SPI command (BIST Read) sent by the MCU, the SPI_G bit is set to 1 as part of the SBC response. Reading the DIAG_SPI register indicates an SPI_CLK error. This is only for the first command with no errors in subsequent SPI transactions. The SPI BIST command (when checked on the DSO) shows 16 clock pulses when CS is low. The command also provides the expected response (LBIST and ABIST1 OK) except for the status of the SPI_G bit.

The SBC datasheet mentions that the SCLK signal should be low outside of active CSB. During startup (before SPI initialization by the MCU), there is a short duration for which the SCLK is high when CSB is inactive. Could this be the reason for the error? Are there any other possible causes?

Would appreciate some help in this regard.

Thanks and Regards,

Vimal

[TomasVaverka]

Hi Vimal,

Having SCLK high for a short duration when CSB is inactive should not be the reason why the SPI_CLK flag is set.

From the datasheet:

Could you please post here a scope shot illustrating the number of clock cycles when CS is low?

Also please verify your SPI configuration and make sure that you have set CPHA=1 (data sampled on the falling edge). 

Best regards,

Tomas

[VN]

Hi Tomas,

Thank you for your response. I checked the clock cycles in the BIST command prior to posting the query and they match the expected number (16). But since SPI_G is the first bit to be transmitted by the SBC, it is my understanding that it indicates an error in a previous SPI transaction. If this is true, it means that the SPI_CLK error was raised for an SPI command issued prior to reading the BIST register. But such a command has not been initiated by the code. This is why I suspected that the issue may be caused by the SBC interpreting the state of the signals on the SPI lines as valid when they are not i.e. prior to SPI initialization by the MCU. Please let me know if my understanding is incorrect.

The SPI is configured so that the MCU receives data on the falling edge of the SPI clock. The response received from the SBC for the BIST command is as expected (except for the SPI error) and all subsequent transactions proceed without SPI errors.

A scope shot with all four SPI signals for the first SPI transaction (BIST Read) is attached for your reference. Please let me know if any other details are required.

Thanks and Regards,
Vimal