FS2633 Reset is always low

[Borden]

Dear Team,
    We are using the power chip MFS2633AMDE4ADR2 to supply power to the S32K396 (BGA289). LDO1 is 3.45V, LDO2 is 5V, and Vpre is 6V, but GPIO1 is low,GPIO2 is high,the RESET pin remains low at all times. Even when connecting the Debug pin to VBOS (debug mode), the RESET pin still remains low. What could be the reason?

[TomasVaverka]

Dear Hongyu,

Please see below the RSTB Low reason checklist.

Please check regulators output when RSTB low with oscilloscope, please also check if there is OV/UV flag reported.

How are your FCCU_CFG[2:0] bits configured? Does it happen if you set FCCU_CFG[2:0] to 0b000 (FCCU monitoring disabled)?

I hope it helps.

BRs, Tomas

[Borden]

Thanks! Does running FS26 in debug mode also affect the RESET? We tested the over-voltage flag VLDO1, which is set to 1 (over-voltage), and the actual voltage is 3.46V. Why is it not 3.3V, and why is it so high?

[TomasVaverka · Accepted solution]

Dear Hongyu,

1. Yes, as in Debug mode, the WD period is infinite (= WD window fully opened) meaning no WD error if no watchdog feed.

2. Could you please share your schematic? Are you using all the recommended caps as shown in the AN12995, chapter 3.6? 

What is the load connected to VLDO1? Can you disconnect it from VLDO1 and observe if the voltage stabilizes at 3.3V? This can help determine if the problem is due to the SBC itself or an external influence.

BRs, Tomas

[Borden]

Dear,

Thank you very much!

1. According to the recommended values, the input and output capacitor designs are satisfied.

2. Following your second suggestion, removed the load from the H-bridge chip in the circuit. VLDO1 returned to normal(3.3V), and the reset function is also operating correctly.

Thanks!!