FS26 Main clock monitoring

[90insu]

For the FS26 main clock monitoring,

1. Is this already implemented in the FS26 hardware, or does it need to be configured/enabled?
2. When this fault occurs, could it also cause the SPI to fail due to the clock failure?
Our MCU communicates with FS26 via SPI, and in some cases where we are not using the FSXB, we would like to check if SPI fault is generated from the clock failure so that MCU can detect the fault without using FSXB. (Not sure if MCU can distinguish, if it would be clock fault or general SPI communication fault, but the intention is to detect the clock fault using SPI.)

[RafaR]

Hello 90insu

Good day!

1.- Is this already implemented in the FS26 hardware, or does it need to be configured/enabled?

The main clock monitoring is implemented in FS26 hardware, but its reaction and reporting are configurable/enabled via OTP and SPI registers.

Details:

FS26 contains an internal main clock and clock supervision logic as part of the fail‑safe state machine (used for MCU monitoring, watchdog timing, SPI supervision, and safety sequencing). This monitoring is always present in silicon; it is not something you have to “add” in software.

2.- When this fault occurs, could it also cause the SPI to fail due to the clock failure?

Yes, a main clock fault can indirectly cause SPI communication to fail, but SPI failure ≠ unambiguous proof of a clock failure.

3.-Our MCU communicates with FS26 via SPI, and in some cases where we are not using the FSXB, we would like to check if SPI fault is generated from the clock failure so that MCU can detect the fault without using FSXB. (Not sure if MCU can distinguish, if it would be clock fault or general SPI communication fault, but the intention is to detect the clock fault using SPI.)

SPI can indicate “FS26 internal fault,” but not uniquely identify clock failure.

I hope this information has helped you, please let me know if you need help with anything else.

Have a great day and best of luck.