MC3377XC CB function measurement by GUI
Many customers need test MC33771/2 cell balancing function, this article will introduce this function test detail step by step by setting in NXP MC3377X GUI.
Below simple diagram shows the internal cell balancing switches arrangement example for MC33772C.
During test also refer to these switches positions to measurement the voltage variation on balancing resistors.
Figure1
For below picture is MC33772C GUI setting,the cell balancing feature is active in Normal, Sleep and Diagnostic modes.
The SYS_CFG1 register contains the CB_DRVEN bit. The CB_DRVEN bit must be
enabled for any of the drivers to be activated. All drivers are disabled when CB_DRVEN
bit is logic 0.
For cell balance drivers to be active, both the SYS_CFG1[CB_DRVEN] and
the CBx_CFG[CB_EN] bits must be set to logic 1.
The individual cell balance timer is set through the CBx_CFG[CB_TIMER].
Timing parameters can be found in the register map of this specification. Each time the cell
balance CBx_CFG[CB_TIMER] bit is written by the MCU controller, the MC33772C
initiates the cell balance timer.
It is important to explicitly mention, each time the CB_DRVEN bit is set to logic 0, then cell balancing timers get reset to 0 (the CBx_CFG[CB_TIMER] bits are unchanged) and all cell balancing MOSFETs are turned off.
Before the CB_DRVEN bit is set again to logic 1, all CBx_CFG registers need to be
configured again.
Otherwise, a cell balancing sequence will be started with the previous
settings.
The SYS_CFG1 register contains the CB_MANUAL_PAUSE bit, which, if set to
logic 1, instructs the MC33772C to disable the cell balance switches.
When the CB_MANUAL_PAUSE bit is set again to logic 0, the cell balance switches are
restored according to the programming.
However, the cell balance timers are not frozen during a manual pause. The contents of CBx_CFG[CB_TIMER] and ADC2_OFFSET_COMP[ALLCBOFF_ON_SHORT] bits must not be changed while balancing.
Figure2
Below are the cell balancing funciton test steps:
1:Customer can select EVB of KIT33772CTPLEVB and 6 cells or BATT-6EMULATOR,according user manual UM11562 to set up this test platform.
KIT33772CTPLEVB: TPL evaluation board for MC33772C | NXP Semiconductors
BATT-6EMULATOR | Battery Emulator for MC33772 | NXP Semiconductors
2:According Figure1 balancing resistors positions to match them in the EVB for expediently measurement.
You can also download KIT33772CTPLEVB schematic from below link:
KIT33772CTPLEVB Schematics
Figure3
Match the Figure1 balancing resistors with about Figure3 green circled parts.
3：Figure2 is the operation on GUI, after correctly connection MC33772 EVB and battery you can accord above explain of CB function to verify or setting related registers.
4：Enable CBDrvEn bit before test this CB function.
For example when testing SW1 ON in the Figure1, it is necessary to enable the CBEN/STS bit of CB_CFG_1, and then test the voltage change of TP235, which will change from 0 to the voltage value of Cell1.
If you use the BATT-6EMULATOR you can slide battery1 channel to change its value for verify this operation.
In the default value the CBDrvEn bit and CBEN/STS bits are OFF.
5：Also in Figure1 when testing SW2 ON, enable the CBEN/STS bits of CB_CFG_1 and CB_CFG_2 simultaneously.
You will find that the value of TP234 will change from the voltage value of Cell1+Cell2 to the value of Cell1.
6：It is also possible to test that the voltage across R1 will change from 0V to the voltage value of Cell2, when only the enable CBEN/STS bit of CB_CFG_2 and also SW2 is enabled.
7: And so on. The subsequent tests will continue until the end
In the test will use the GUI which can be downloaded from below link:
：
https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM33772BSPIEVB
記事全体を表示
