work with processor registers?

[jackrubby]

Hi,

I am working on p1022 with a sample designed board. I want to use only SATA and Ethernet processor features and I put a sd card with minimal image.

1- Should I modify registers content to use these features? or primary initialize features is adequate?

2-  How can I read/write registers? Is CodeWarrior only way ?

3- For example in Protocol Control Register (PROCTL), DTW bits are 00 at first.How can I change DTW to 01 for 4-bit data transfer rate in eSDHC? Is it possible before booting minimal image?

Thanks.

[marius_grigoras]

Hi,

Can you tell us what do you need more exactly? To boot up a Linux on your P1022 board via SD card? In positive case, you should have an u-boot on the SD card, the DIP SW settings set up for booting up from ESDHC and after the u-boot is up and running you can start to boot the linux image.

Sure, you can make u-boot and Linux debug using CW (you can have access to stack, variables, memory view, both memory-map and core registers, break-points and so on).

About SATA and Ethernet features...these are already included in the SDK Linux image.

Regards,

Marius

[jackrubby]

Thanks a lot Marius.

Yes, I want to boot up a Linux on P1022 via SD card. So, I do not need CW for boot up according to your comments.

[marius_grigoras]

Yes, I confirm that you don't need CW for booting up the board. A linux machine is enough for mounting the SD card and to write your images.

Marius

[jackrubby]

Thank you.

If I change core registers, will changes stay in next boot up ? or if it starts in next boot up a Linux image, will changes remove?

[marius_grigoras]

At any booting up procedure, system reset is triggered, so both core and memory mapped (processor) registers will be set up to the default values (you can look in the reference and core manuals for these values).

Regards,

Marius

[jackrubby]

For example, If I want to enable ECC, I will set ECC_EN by CW. How can I have ECC enable forever?

[marius_grigoras]

You'll need to put this setting in the u-boot code and during booting time this setting will be set up.

Marius

[jackrubby]

Should I put every setting in the u-boot? How can I do this?

[marius_grigoras]

You must get familiar with our last Linux SDK 1.4 [1] (contains also the u-boot support). You can find the documentation here [2]

I suggest you to put the the register settings in the last stage, just after u-boot relocation in DDR.

[1] Linux® SDK for QorIQ Processors Product Summary Page

[2] Freescale Technical Information Center

[jackrubby]

I am working with Linux SDK 1.3, is it necessary to get SDK 1.4 ?

I am familiar with setting some variables in u-boot before boot up Linux image, but I have not set any core registers up to now. How can I do this? Is it similar with setting variables? what do you mean with last stage?

[marius_grigoras]

Every time our suggestion is to use the last software/tools just to have the latest support in place.

You need to add your code in the u-boot files and re-compile it.

About core registers setup, please take a look in the u-boot files how mtspr/mfspr instructions are used.

Also, I suggest to put your code after pre-early u-boot initalization, maybe cpu_init_r() or/and board_init_r() functions are the best places to used.

Regards,

Marius

[jackrubby]

How can I set or reset GPIOs? Is there any drivers for initializing GPIOs?

And how can I send and receive data by SPI?

[marius_grigoras]

You can interact with SPI flash from u-boot command line using sf command:

=> sf

sf - SPI flash sub-system

Usage:

sf probe [[bus:]cs] [hz] [mode] - init flash device on given SPI bus

                                  and chip select

sf read addr offset len         - read `len' bytes starting at

                                  `offset' to memory at `addr'

sf write addr offset len        - write `len' bytes from memory

                                  at `addr' to flash at `offset'

sf erase offset [+]len          - erase `len' bytes from `offset'

                                  `+len' round up `len' to block size

sf update addr offset len       - erase and write `len' bytes from memory

                                  at `addr' to flash at `offset'

About GPIO support in SDK please take a look in documentation. Second link from above email.

[jackrubby]

Thanks a lot Marius for your answers,

I looked in documentation that you mentioned above. In i.MX processors section, there are some useful information for GPIOs like GPIO programming (read and write mode) and IOMUX Controller. But in QorIQ processors section, there isn't any useful information for GPIO programming. How can I read and write each GPIO pin? or set and reset it?

[marius_grigoras]

Hi,

I never played with the GPIO registers, but I found some code for 9132QDS board.

See below for the function toggling GPIO2. Maybe you can use something similar in your code and call in appropriate places:

static void dbg_io_trig()

{

       // SC3850 Core View To Power Architecture CCSR: 0xFEF0_0000

       volatile UINT32 * Guts_Pmuxcr3           = (volatile UINT32 *)(0xFEFE0068); // GUTS_PMUXCR3: Alternate Function Signal Multiplex Control Register 3

       volatile UINT32 * Gpio1_Gpdir = (volatile UINT32 *)(0xFEF0F000); // GPIO1_GPDIR: GPIO1 direction register

       volatile UINT32 * Gpio1_Gpdat = (volatile UINT32 *)(0xFEF0F008); // GPIO1_GPDAT: GPIO1 data register

// Enable GPIO[2]: USB_TIMER1 FIELD [BITS 22-23]set to "01"

*(Guts_Pmuxcr3) = 0x100;

// Set Direction for GPIO[2] to Output: FIELD DR2 [BIT 2] set to '1'

*(Gpio1_Gpdir) = 0x20000000;

// Set GPIO[2] to '1': FIELD D2 [BIT 2] set to '1'

*(Gpio1_Gpdat) = 0x20000000;

// Set GPIO[2] to '0': FIELD D2 [BIT 2] set to '0'

*(Gpio1_Gpdat) = 0x00000000;

}

Regards,

Marius

[marius_grigoras]

Please note 9132 SoC supports both SC and PA cores, so the above  code is run up from SC core perspective, so if you need something similar but from PA side, you'll need to change the CCSRBAR base to your default SoC CCSRBAR. I think for P1022 is 0xff700000.

Marius

[jackrubby]

Is there only QorIQ Qonverge BSC9132QDS - Fact Sheet documentation for 9132 ?!

I couldn't find any useful documentation for 9132 to look at address registers. which documentation illustrate address values completely?

[marius_grigoras]

The BSC9132 reference manual is still under NDA and is not publicly available. You can contact your sale representative to NDA access to the document.

Regards,

Marius

[jackrubby]

Hi Marius,

According to your given code for GPIOs, I wrote a similar code that it is :

#include <stdint.h>
#include <stdio.h>

static void dbg_io_initial()

{
// e500 Core View To Power Architecture CCSR: 0x0_FF70_0000

volatile uint32_t * Guts_Pmuxcr = (volatile uint32_t *)(0xFF7E0060);   // GUTS_PMUXCR: Alternate Function Signal Multiplex Control Register
volatile uint32_t * Gpio3_Gpdir = (volatile uint32_t *)(0xFF70F200);     // GPIO3_GPDIR: GPIO3 direction register

volatile uint32_t * Gpio3_Gpdat = (volatile uint32_t *)(0xFF70F208);    // GPIO3_GPDAT: GPIO3 data register

// Enable GPIO3[10]: IRQ_DEBUG1_GPIO FIELD [BIT 26] set to "1"

*(Guts_Pmuxcr) = 0x00000010;

// Set Direction for GPIO3[10] to Output: FIELD DR10 [BIT 10] set to '1'

*(Gpio3_Gpdir) = 0x00200000;

// Set GPIO3[10] to '0': FIELD D10 [BIT 10] set to '0'

*(Gpio3_Gpdat) = 0x00000000;
}

int main(){
    dbg_io_initial();
    return 0;
}

I run this code on P1022, but Guts_Pmuxcr couldn't been initialized. I got segmentation fault.

Do I have to write codes in kernel level?  or write a driver?