phy reset time out ,no ethernet link

longqiluo · ‎02-15-2017

hello,I am confusing about 1000M ethernet connection. my CPU is p1023, phy is ar8035, the schemitic is largely same as P1023 reference schemetic. At present stage, I can boot linux nomally. I try to use FM1@DTSEC1 as ethernet device in uboot prompt,but it seems present no link. I can test stable 25M clock from AR8035 pin clk_25M,and I can access the register of phy ,so I think the hardware is ok.When uboot booting, there always present "phy reset time out", does it means the reset of phy have problem or some configuration I am not awared? Detail problem see attached.

Attachment: POWER_V2.PDF is about phy 8035 designing

P1023designing_v4 is about CPU side

PHY_PRO.txt is about uboot log and linux log and some environment variable setting.

DEVDISR.jpg and PORDEVSR.jpg are register of P1023 ,regarding to DTSEC setting and power-on status.

could anybody analysize for me? thank you in advance! if you have any information which could be help, please send my email: [email protected]

Original Attachment has been moved to: PHY_problem.rar

ufedor · ‎02-16-2017

> I can test stable 25M clock from AR8035 pin clk_25M

How the DTSEC is configured?

Note that for 1000M operation the RGMII clock has to be 125MHz.

longqiluo · ‎02-16-2017

Yeah, the DTSEC1 is configured as RGMII mode(you could see the register

DEVDISR,PORDEVSR) , the phy power -on strapping as attached . I do test 25MHz

clock ai pin CLK_25M, as you mentiioned, it should be 125M.So, please help me

check the schemitic about PHY ar8035(though it is the same as your offical

shemetic).

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ufedor Ð´:

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Re: phy reset time out ,no ethernet link

reply from ufedor in QorIQ Processing Platforms - View the full discussion

> I can test stable 25M clock from AR8035 pin clk_25MHow the DTSEC is

configured?Note that for 1000M operation the RGMII clock has to be 125MHz.

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ufedor · ‎02-16-2017

In the PHY datasheet it is written:

"NOTE: CLK_25M default outputs 25MHz, can be configured to 50MHz, 62.5MHz, or 125MHz by register MMD7 8016[4:3]."

Have you did the configuration?

longqiluo · ‎02-16-2017

no, I have not set MMD7 8016[4:3] , your advises could be considered. Except

this, I found the ethaddr=00:04:9F:02:87:0D, in AR8035 DATASHEET, it describles

the registers about local MAC address,as attached. Should i set it as ethaddr=

00:04:9F:02:87:0D ?:=> pribaudrate=9600bootargs=root=/dev/mtdblock2

rootfstype=jffs2 rw console=ttyS0,9600bootcmd=bootm 0xefb70000 -

0xeda50000bootdelay=3bootfile=uImageeth1addr=00:04:9F:02:87:0Dethact=

FM1@DTSEC1ethaddr=00:04:9F:02:87:0Cethprime=FM1@DTSEC1fman_ucode=

0xec000000gatewayip=192.168.1.1hwconfig=usb1:dr_mode=host,phy_type=ulpiipaddr=

192.168.1.19loadaddr=0xec002000serverip=192.168.1.20stderr=serialstdin=

serialstdout=serial

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ufedor Ð´:

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Re: phy reset time out ,no ethernet link

reply from ufedor in QorIQ Processing Platforms - View the full discussion

In the PHY datasheet it is written:"NOTE: CLK_25M default outputs 25MHz, can be

configured to 50MHz, 62.5MHz, or 125MHz by register MMD7 8016[4:3]."Have you

did the configuration?

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ufedor · ‎02-16-2017

> Except this

This is not needed.

longqiluo · ‎02-17-2017

dear engineer, I tried to write MMD7 8016[4:3], but itdoesn't work. i think

maybe my write operation is not right. here is my operation in uboot prompt:U-

Boot 2011.12-00064-gbfb0c9a-dirty (Feb 13 2017 - 20:29:47)

CPU0: P1023E, Version: 1.1, (0x80fe0011)Core: E500, Version: 5.1, (0x80212151)

Clock Configuration: CPU0:400 MHz, CPU1:400 MHz, CCB:266.667 MHz,

DDR:400 MHz (800 MT/s data rate) (Asynchronous), LBC:16.667 MHz

FMAN1: 266.667 MHzL1: D-cache 32 kB enabled I-cache 32 kB enabledBoard:

P1023 RDSI2C: readySPI: readyDRAM: 256 MiBFlash: 64 MiBL2: 256 KB

enabledNAND: fsl_elbc_nand: address did not match any chip selects0 MiBEEPROM:

Read failed.PCIe1: Root Complex of Slot 1, no link, regs @ 0xff60a000PCIe1: Bus

00 - 00PCIe2: Root Complex of Slot 2, no link, regs @ 0xff609000PCIe2: Bus 01 -

01PCIe3: Root Complex of Slot 3, no link, regs @ 0xff60b000PCIe3: Bus 02 - 02In:

serialOut: serialErr: serialNet: Fman1: Uploading microcode version

160.0.18PHY reset timed outFM1@DTSEC1 , FM1@DTSEC2Hit any key to stop

autoboot: 0 => mii infoPHY 0x05: OUI = 0x1374, Model = 0x07, Rev = 0x02,

1000baseX, HDXPHY 0x08: OUI = 0x0000, Model = 0x00, Rev = 0x00, 1000baseX, HDX=&

gt; mii write 0x05 0x0d 0x07=> mii write 0x05 0x0e 0x8016=> mii write

0x05 0x0d 0x4003=> mii read 0x05 0x0e 0000=> mii write 0x05 0x0e

0x0018=> mii read 0x05 0x0e 0000=> attachment is recommended in

AR8035 DATASHEET.please help me£¡ thank you !

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ufedor Ð´:

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Re: phy reset time out ,no ethernet link

reply from ufedor in QorIQ Processing Platforms - View the full discussion

> Except thisThis is not needed.

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ufedor · ‎02-17-2017

Possible reference is function fecmxc_mii_postcall(int phy) in the:

Cross Reference: /denx/u-boot/board/freescale/mx6qarm2/mx6qarm2.c

longqiluo · ‎02-17-2017

thank ufedor, I followed you advises and now I can get 125M ai CLK_25M pin.but

still no link .I refered to the uboot -2011.12 source uboot/board/freescale/

p1023rds/p1023rds.c there is a statement:int board_eth_init(bd_t *bis)

100{

101 ccsr_gur_t *gur = (ccsr_gur_t *)CONFIG_SYS_MPC85xx_GUTS_ADDR;

102 struct fsl_pq_mdio_info dtsec_mdio_info;

103

104 /*

105 * Need to set dTSEC 1 pin multiplexing to TSEC. The default setting

106 * is not correct.

107 */

108 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TSEC1_1);

109

110 dtsec_mdio_info.regs =

111 (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;

112 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; So , does the pmuxcr set as

MPC85XX_PMUXCR_TSEC1_1(0X10000000)? if does, the multiplexing is wrong, how

should I modified?

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ufedor 写:

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Re: phy reset time out ,no ethernet link

reply from ufedor in QorIQ Processing Platforms - View the full discussion

Possible reference is function fecmxc_mii_postcall(int phy) in the:Cross

Reference: /denx/u-boot/board/freescale/mx6qarm2/mx6qarm2.c

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ufedor · ‎02-18-2017

PMUXCR[TSEC1_1] should be set to 1.

longqiluo · ‎02-18-2017

thank ufedor. Actually, I already set PMUXCR[TSEC1_1]=01, and PMUXCR[TSEC1_2]=

01, so read the PMUXCR(addr=0xff60_0000 + 0x00e0_0060=0xffe0_0060) =0x1400_0000,

like below :U-Boot 2011.12-00064-gbfb0c9a-dirty (Feb 18 2017 - 14:58:40)