RXRDY and TXRDY are exposed in the UDSRn register. They are not connected to the DMA controller. The talk about DMA is legacy from the original UART chips where these lines could be connected to a DMA controller (but usually weren't).
P2041 does not support connecting rxrdy/txrdy to the DMA engine. It is possible to do I/O at 115200 bps without losses, using the FIFO and interrupts. You should debug to find out what is stopping the CPU from handling the interrupt in a timely fashion, or processing the received data fast enough, etc.