Problem PCI RC Read_Configuration_Ready_Register from EP

[zy_mooncity]

There are two P2020 boards in my system, one is configured as PCI root complex, and the other is configured as endpoint . The CFG_READY bit of the Read_Configuration_Ready_Register is set once the EP initialization is completed, and the PCI read operation on the EP shows the CFG_READY bit is 1.

On the PCI root complex, I want to know if the CFG_READY bit of the EP is set or not, then I try to read the Read_Configuration_Ready_Register from the RC, but the result is always 0. I read Advanced_Error_Reporting_Capability_ID_Register in the same, the expected result is returned (0x0001).

Is possible to get the value of Read_Configuration_Ready_Register on the EP from the RC?

[yipingwang]

Hello Zuo Yun,

EP should run prior RC in order to initialize PEXIWARn and PEX_CFG_READY[CFG_READY], otherwise BARn is not write-accessible for RC.

CFG_READY is set when in EP mode, then the host can start the enumeration process. The transaction layer handles configuration requests from external hosts only after the CFG_READY bit is set.

So no need to read CFG_READY on EP from the RC.

Have a great day,
TIC

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