POR configuration registers P1010

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POR configuration registers P1010

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smirnovalexey
Contributor I

Hello.
Trying to make some simple design using this processor.
There are two ways to achieve POR configuration. One is to use pull-ups and pull-down resistors. Another is to use PLD (CPLD for example)
Can you please point me out to a simple scheme how can I use POR resistors and at the same time having other signals there during normal process operation.

For example during boot the pin IFC_AD_00/cfg_sys_pll_0 should configure cfg_sys_pll_0 using resistor. And after booting (READY/TRIG_OUT is set) it hould be IFC_AD_00.

Hope i am clear here.

Thank you and have a great day.

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alexander_yakov
NXP Employee
NXP Employee

Yes, several device pins act as configuration pins during power on reset (POR). This switching between normal function and POR function of the pin is done automatically - during POR period internal output driver is disabled (switched to high impedance mode), and pin becomes input pin, the state of this input pin is internally sampled and used as POR configuration value.

According to device datasheet, Section 3.9, most of the configuration pins have internal on-chip pull-up resistor of approx 20 Kohm value, so if you wish to pull this pin up, this internal pull-up may be enough. If you wish to pull this pin down, datasheet states 4.7Kohm pull-down resistor will be enough to overpower internal weak pull-up.

Note that this depends on external load. If you have heavy external load connected to POR pin, internal weak pull-up may be not enough to create logic "high" state during POR configuration. In this case you may add external pull-up to be sure.

When the device comes out from reset, and appropriate pins become outputs and actively driven, these externally connected pull-ups/pull-downs should not significantly affect output driving capability of the device pins, because 4.7K is approx 100 times less than typical output impedance of the output driver.


Have a great day,
Alexander

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