PCIe Link Bandwidth Management Notification capability.

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PCIe Link Bandwidth Management Notification capability.

Contributor I

I'm working with p4080 and t1040 platforms and I'm curious how the Link Bandwidth Management Notification capability works.

The documents for both these SOCs state that the "Link Bandwidth Notification Capability" bit is set in the "Link Capability" register.  This capability is also supported in various PCIe switches that I have connected to these CPUs.  Since this feature is supported I believe I can set the "Link Bandwidth Management Interrupt Enable" on the CPUs and Switches.  Once enabled, if any PCIe bus should reconfigure and downgrade itself (lower speed or less links) I will get an interrupt that lets me know that the system is not operating at its designed potential.

However all PCIe documentation vaguely refers to this as an "Interrupt." I'm wondering how this interrupt manifests itself on the SOCs?  I've looked at the TLP formating for PCIe messages and nothing jumps out at me.  Does it result in a Non-Fatal PCIe Error?

I already have an error ISR that responds to Correctable, Fatal, and Non-Fatal PCIe errors.  If this ISR goes off should it also search the PCIe topology for a link that might have re-trained?

Thanks for any help.


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NXP Employee
NXP Employee

Hello Samuel Stearley,

There are two ways to notify the software that link bandwidth has changed:

      Push model – through interrupt

      Pull model – through polling of status bits.

"Push model" is selected for P4080/T1040. The software can poll the status of PCI Express Link Status Register—0x5E[LABS/LBMS] to monitor the changes. The implementation is compatible with PCIe spec 2.0.

Have a great day,

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