P4080DS System Clock Speed

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P4080DS System Clock Speed

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yaseryurtcan
Contributor II


Hi,

I want to change the system clock speed. However, to do that I need to change SW3 6-8 bits(Default 100). When I change from 100 to 110 which is 125 MHz, the system could not boot. Please find the output in the attachment.

Then I have tried all combination, the result is that I can cont increase system clock more than 100MHz.However I can decrease to 75 MHz. So why does system clock speed inrease? How can I increase that?

Best regards.

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yyurtcan
Contributor III

Hi,

After you stated that I need to change RCW  values in order to achieve higher frequency of CPU, CCB, DDR, and Elbc bus, I want to keep other RCW values and SYSCLK the same and change CPU clock frequency by changing RCW[CC1_PLL_RAT] either from 01111(which is 15:1, 1,5 GHz) to 10000 (which is 16:1, 1,6 GHz) or from 01111(which is 15:1, 1,5 GHz) to 01100 (which is 12:1, 1,2 GHz). In both cases, the demo board could not boot. Why is the reason for that? Basically I want to keep CPU, and CCB clock frequency the same, but increase DDR clock frequency to 1300 MHz and ELBC to 133 MHz. To do that what are the steps that I should follow? I think that I need to change SYSCLK and RCW(I don’t know which part I change in RCW. Could you provide new RCW for that?).

Best regards.

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r8070z
NXP TechSupport
NXP TechSupport

>Is this right?

No I wrote that you already has maximum of the platform clock frequency you cannot increase eLBC clok by sysclock frequency increasing. I.e. at sysclock=100MHz you ypu already got the platform clock maximal.

>But I can increase CPU, CCB and DDR clock by increasing system clock

You over clocked device, it may operate incorrectly (as you could see) or even can be damaged due to extra power consumption.

>Second question I want to reduce  read access time to NOR FLASH so that decrease boot time.

>Is there any other way for that?

I do not see simple way. Check your bootlader, if it first load small piece code  to the memory which than re-programs the eLBC NOR bank to load the rest with maximal possible rate. Or use the PBL to configure the eLBC NOR bank to the maximal possible read rate.

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yaseryurtcan
Contributor II

To make sure that as you stated increasing system clock does not increase elbc clock which is derived from the platform clock. Is this right? (But I can increase CPU, CCB and DDR clock by increasing system clock). As far as I know system clock determine platform clock which is determine elbc clock. So, My knowledge would be wrong now.

Second question I want to reduce  read access time to NOR FLASH so that decrease boot time. Is there any other way for that?

Best regards.

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r8070z
NXP TechSupport
NXP TechSupport

The eLBC clock is derived from the platform clock (can be 1/8, 1/16, 1/32). So because you already has maximum of the platform clock frequency you cannot increase eLBC clok by sysclock frequency increasing.

The LCRR register (LCRR[CLKDIV]) controls eLBC clock:

“CLKDIV  Clock divider. Sets the frequency ratio between the platform clock and the local bus clock. Only the values shown below are allowed. Note that the reset value of CLKDIV depends on the RCW source configuration(cfg_rcw_src[0:4]).

00000-00001 Reserved

00010 8

00011 Reserved

00100 16

00101-00111 Reserved

01000 32

01001-11111 Reserved

NOTE: It is critical that no transactions are being executed via the local bus while CLKDIV is being modified. As such, prior to modification, the user must ensure that code is not executing out of the

local bus. Once LCRR[CLKDIV] is written, the register should be read, and then an isync should be executed.”

Take into account that the specifications limit eLBC clock to 100 MHz.

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yaseryurtcan
Contributor II

Hi,

As far as I understoond, I need to change CPU,CBU and DDR max clock frequency vaules in RCW in order to meet system requirement when I change SYSCLK from 100 MHz to 125 MHz. I have checked RCW but I could not find where to change in RCW (I have not deep knowledge about RCW). One last question, I want to increase SYSCLK to achieve the higher ELBC frequency so that NOR FLASH read access time will decrease. Is this a good way? Does this violate other the system operation?

Best regards.

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r8070z
NXP TechSupport
NXP TechSupport

Have a great day,

According to the P4080 QorIQ Integrated Processor Hardware Specifications, for the fastest P4080 device max CPU frequency is 1500 MHz, max CCB frequency is 800 MHz, max DDR clock frequency is 667 MHz. As I can see for the Reset Configuration Word (RCW) which you used these values is achieved at sysclock frequency = 100 MHz. I.e. when you simply increase sysclock to 125 MHz you violate the P4080 specifications. If you want to use 125 MHz then you should change the RCW fields which define CPU, CCB and DDR frequencies in way which satisfies the P4080 specifications.

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