I'm designing local bus interface from P2041 processor to some Flash and nVSRAM parts. In the QorIQ P2040 Reference Manual, Rev 4 section 13.4.2.3.4, it states that the LOE_B asserts and negates on the rising edge of the bus clock, but this conflicts with the waveforms in Figures 13-14, 13-15 where it is shown changing on falling edge of clock. Which is correct? Thanks, Grady
Reference Manual figures are for illustration purposes only. Please look P2041 Hardware Specifications, Figure 22 for exact reference point from which LOE assertion/negation is measured, and Table 51 for delay values.
Have a great day,
Alexander
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