Looking at AN4261 (rev4).
In Table 12, do the min and max DDR memory bus clock speeds apply to the asynchronous mode of operation only?
For example, lets say we want DDR3 memory. In asynchronous operation, we provide an external clock (lets say 100MHz) and according to Table 16 we can scale it 6:1 or 8:1 to provide a DDR data rate from 600MHz to 800 MHz?
But if we run in synchronous mode, our memory bus runs at half the Platform Frequency. Lets say our platform frequency is 512 MHz, out memory bus will be clocked at 256MHz. This is outside the limit of what is specified in Table 12 for DDR3 memory bus clock speed.
I believe that the minimum clock limitation in the Table 12 is originated by SDRAM devices because the P2020 Hardware Specifications contains timings for 200 MHz bus clock.
> Lets say our platform frequency is 512 MHz, out memory bus will be clocked at 256MHz.
Is my understanding correct that your intention is to violate the DDR3 SDRAM JEDEC Specification?
I'm asking because specified maximum tCK period is 3.3 ns.
I just saw that the minimum clock frequency for DDR3 according to the JEDEC specification is 300MHz. Would the following be a correct statement:
"In order to use DDR3 for the P2020 in synchronous mode, we have to use a 100MHz SYSCLK and choose a Platform to SYSCLK ratio of 6:1?
To achieve faster rates of DDR3 for the P2020, we would have to run in asynchronous mode as dictated by Table 19 in AN4261 rev4."
Usually it is inconvenient to explicitly describe all possible use cases and Design Checklist contains basic recommendations and constraints. Engineers are capable to correctly implement any specific design in this case.