P2010 - PLLs problem

[marcosantos]

In my board, the P2010 has problems with the internal PLLs. The SYSCLK is 66.6666MHz and the CCB ratio is 8:1 but I get about 1GHz at the CLK_OUT pin if I select in GUTS_CLKOCR=0x80000000. What is even more strange is the I got about 58MHz at CLK_OUT pin if I choose GUTS_CLKOCR=0x80000003 and not 33MHz. What is even more stange is that the 8:1 ratio of the CCB should be 533MHz (8x66=533) but if I choose the 4:1 CCB ratio I got 533MHz! Another very strange thing is that the GUTS_PORPLLSR register shows correct ratios but the clocks doesn't match what the register says. But, the GUTS_PORPLLSR register also has some strange things. In the reference manual the figure of this register shows 5 bits for the DDR_RATIO but the describing text shows 6 bits.

Anyone where experience a similar problem? I already check every clock, voltage and bootstrap and every thing looks okay.

[marcosantos]

Great new! I've found what was the problem.

The problem was that the clock source of the SYCLK pin was not compliant with the specifications of the rise/fall time required for the P2010. Changing the clock buffer with a better rise/fall time the problem was solved. Now the CPU works as expected and every options work as required.

[lunminliang]

Please see below comment from technical support:

Please confirm that when cfg_sys_pll[0:2]=011 the GUTS_PORPLLSR[Plat_Ratio]=01000.

Please provide the processor connection schematics for inspection as searchable PDF. (You can send direct message to me for this part)

DDR_Ratio field has 5 bits. Please take into account the last 5 digits in the description.

[marcosantos]

I verified that if cfg_sys_pll[0:2]=011 then GUTS_PORPLLSR[Plat_Ratio]=01000.

[lunminliang]

It could be helpful to provide the processor connection schematics for inspection as searchable PDF. Direct message could be used.