P1025 dma request timing

[PaulWalker]

Hi,

I am using DMA to transfer data via the eLBC on P1025. I want to look at the time difference between setting CS (start transfer) and CB (transfer in progress) being set. Is there any information regarding this timing? I am particularly concerned with the nominal time and maximum boundary.

Note: we have a custom DMA driver (within an RTOS) that checks for CB=1 after CS=1; to verify job submission. Sometimes the driver misses the CB=1 event and assumes an error. If we interrupt lock the code between CS=1 and CB=1 it's ok, but I want to minimise the potential interrupt lock period.

Kind regards,

Paul

[ufedor]

Please refer to the P1025 QorIQ Integrated Processor Reference Manual, 2.2.1 Accessing CCSR memory from the local processor:

"To guarantee that the results of any sequence of writes to configuration registers are in

effect, the final configuration register write should be chased by a read of the same

register, and that should be followed by a SYNC instruction. Then accesses can safely be

made to memory regions affected by the configuration register write."

Please implement this sequence for the DMA_MR before checking the DMA_SR[CB] state.

[PaulWalker]

Hi, thanks for reply.

Yes, the method you give is already being done.

My system is under fairly heavy interrupt load due to Ethernet traffic, and others. I suspect the DMA register write/read sequence is occasionally being interrupted so need to prevent interrupts for a short period. We also note that CB=1 is not always set on the first register read after CS=1. Thus I want to know the maximum limit to wait for CB=1 or give error - 5 register reads, 10 register reads, 1 microsecond, etc.

Kind regards,

Paul

[ufedor]

> Yes, the method you give is already being done.

The sequence described in the RM definitely works.

Please doublecheck your code.

[PaulWalker]

Hi, thanks again for reply.

I think my query is a little mis-understood. I am not questioning the correctness of the sequences described in the RM. My query concerns only characteristic timing information which I cannot find in any of the available documentation.

Specifically, with reference to P1025RM Rev1 section 13.4.1.2.3 (basic chaining mode), do you have any characteristic timing information between steps 5 and 6? I am mostly concerned with the maximum time. This is required to aid establishing reasonable error handling in software.

Kind regards,

Paul

[ufedor]

If some timing is required it is explicitly stated in the processor's RM and HS.

There are no timing requirements in the sequence in question. The clear and set bit sequences should be implemented as described in the P1025 QorIQ Integrated Processor Reference Manual, 2.2.1 Accessing CCSR memory from the local processor.