The device does not have so much boot options, it has only power-on reset sequence and hard reset sequence. According to Section 4.5.1.2 of P1021 Reference Manual, these two reset types are equivalent. However, as long as hard reset is initiated after assertion of HRESET_B input, in case if this input is driven by external logic in your design, I think it is possible to implement this external logic in way in which it can be later read to understand that HRESET_B input was asserted.
HRESET_B input is typically asserted by external logic in response to HRESET_REQ assertion by device. The reason, why this output was asserted, can be determined by reading GUTS_RSTRSCR register, but this register is cleared by HRESET_B, so this reading should be performed before HRESET_B is asserted, and the result should be stored somewhere outside of the device before applying HRESET_B.
Soft reset option is also available, but it generates only machine check interrupt to the core. The reason of machine check interrupt may be determined by reading GUTS_MCPSUMR.
Have a great day,
Alexander
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