LGTA question

[sapril]

I have a P1011 with a local bus configured to use an external LGTA (SETA=1).

I am accessing a third party FPGA with a 16-bit address bus however, the FPGA registers are 32 bit.

Each valid 32-bit read access to this FPGA produces two back-to-back LGTAs as expected - DWORD read. 

An invalid 32-bit read access to this FPGA (invalid register address) produces a single LGTA.  The second LGTA never gets asserted.

In my case, the bus transaction appears to have completed successfully with that single LGTA.  There is no bus error indicator from the bus error monitor which is set to a 2.6 s timeout.  From a SW perspective the read is unit32_t.  The read appears to have completed successfully but the data is unreliable.  

Under what circumstances would the P1011 be happy terminating a DWORD read with only a single LGTA? 

[LPP]

>a third party FPGA with a 16-bit address bus

Did you mean 16-bit data bus?

>An invalid 32-bit read access to this FPGA (invalid register address) produces a single LGTA.

Have you a reason to perform access to invalid register address?

>the bus transaction appears to have completed successfully with that single LGTA.

Can you investigate this access using a scope or LA? You migh see very long duration of the second back-to-back access. When LGTA is not asserted, the transaction is terminated by bus monitor timeout and an error is reported in eLBC_LTESR[BM]. If bus monitor is disabled eLBC_LTED[BMD]=1 then internal bus time-out still occurs but the error is not reported.

>Under what circumstances would the P1011 be happy terminating a DWORD read with only a single LGTA?

I think, you should avoid this condition (for example, use 16-bit reads instead). Bus monitor timeout is destined to handle error cases. Don't use timeout termination for normal practice. eLBC is quite robust to cope with this condition but aLBC stays blocked till the end of the transaction and no other accesses could be executed.

[sapril]

>>a third party FPGA with a 16-bit address bus

>Did you mean 16-bit data bus?

Yes

>>An invalid 32-bit read access to this FPGA (invalid register address) produces a single LGTA.

>Have you a reason to perform access to invalid register address?

Yes, there is a bug where approx. every 12 hours we think we get an invalid access to this fpga.  The fpga has a wd timer that will produce its own LGTA in the event of an invalid access.  I want to shut off that wd timer so that I can use the P1011 bus monitor to catch the invalid access.  Unfortunately when I shut off the wd timer in the fpga it still produces a single LGTA on a dword access.  I have asked the fpga vendor to fix this problem but I want to understand why the processor appears to be happy terminating a dword access with only one LGTA.  

>>the bus transaction appears to have completed successfully with that single LGTA.

>Can you investigate this access using a scope or LA? You migh see very long duration of the second back-to-back access. When LGTA is not asserted, the transaction is terminated by bus monitor timeout and an error is reported in eLBC_LTESR[BM]. If bus monitor is disabled eLBC_LTED[BMD]=1 then internal bus time-out still occurs but the error is not reported.

Yes, I have connected a LA and I can see that only one LGTA is produced, and no error from the bus error monitor.

>>Under what circumstances would the P1011 be happy terminating a DWORD read with only a single LGTA?

> I think, you should avoid this condition (for example, use 16-bit reads instead). Bus monitor timeout is destined to handle error cases. Don't use timeout termination for normal practice. eLBC is quite robust to cope with this condition but aLBC stays blocked till the end of the transaction and no other accesses could be executed.

Right, we don't want this to happen but we have a bug where it does happen approx every 12 hours.  I want to catch this error with the bus monitor but as long as there is one LGTA from this fpga during an invalid access it appears it wont catch it.  I am not sure why a single LGTA can terminate the cycle unless perhaps the transaction from the processor is not an atomic operation, or that out-of-order transactions are allowed.  I couldn't find a guard bit in this processor manual, which is a bit from older PPC families that allowed me to force guarded transactions.

[LPP]

It seems the problem requires deeper investigation.

I would like to see LGTA/LCS/LALE waveforms of the failed access.

I guess the FPGA asserts LGTA for long time so that it can prematurely terminate the subsequent back-to-back access. In this case,  the bus monitor is not to blame.

Can you create a Service Request to our technical support?

[sapril]

Thsi problem turned out to be a second LGTA that came out of the FPGA at a time that was less than the bus monitopr timeout.  I could exploit this by making the bus monitor timeout smaller, or by putting a logic anylzer on the signal.  Problem solved.  The P10xx will not terminate a dword access based on one LGTA.  It requires both.