How to adjust DDR3 parameters on P1020

[YanjunLuo]

Hi there,

I'm design a new P1020 board based on P1020RDB-PC, I use P1020NSN2HFB so the DDR3 can run at 667MHz data rate. I found that U-BOOT can always boot up, but the kernel can't. the kernel always meet machine check. I know P1020RDB-PC use a slower DDR3 the rate is 1333MHz, I only can use the 1600MHz one. Does anybody know how to adjust the DDR3 controller to make it work?

Regards,

Yanjun Luo.

[r8070z]

Have a great day,

It is supposed that U-Boot initializes the DDR controller and reports the correct memory size to Linux, so that Linux is capable of using the DDR memory. After DDR controller initialization u-boot relocates itself to RAM memory. So if U-Boot can always boot up we may assume that DDR configured correctly. You can check the DDR memory under U_Boot without Linux. There are U-Boot memory command mtest - simple RAM test. Note, this command may crash the system when the tested memory range includes areas that are needed for the operation of the U-Boot firmware (like exception vector code, or U-Boot's internal program code, stack or heap memory areas).

DDR controller parameters you can change in the uboot/include/configs/p1_p2_rdb_pc.h

Many DDR controller parameters can be configured based on timing parameters that come directly from the manufacturer’s data sheet when using discrete DDR memory components and from the SPD EEPROM of a DIMM module.

“[PATCH] powerpc/85xx: Add support for new P102x/P2020 RDB style boards” says for P1020RDB_PC: “As these boards use soldered DDR chips not regular DIMMs, an on-board EEPROM is used to store SPD data. In case of absent or corrupted SPD, falling back to timing data embedded in the source code will be used. Raw timing data is extracted from DDR chip datasheet. Different speeds of DDR are supported with this approach. ODT option is forced to fit this set of boards, again because they don't have regular DIMMs.”

So if you have implemented on-board EEPROM too, then you should change parameter in the EEPROM.

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[YanjunLuo]

Thanks for your reply. The DDR parameters are saved in the head of the u-boot.bin. I use the boot_format tool to add it, and the config file I modified from config_ddr3_1gb_p1_p2_rdb_pc_667M.dat. I also got the tool for DDR parameters from FAE, the tool's name is RegCalc_only_DDR3_Rev8.xlsm. But it still doesn't work.

And yes the u-boot works, this means the basic memory is ok, but for Linux kernel, it need heavy memory access.  I did the u-boot's mtest for several hours, no problem at all, but the Linux kernel still doesn't work.

Regards,

Yanjun Luo.

[r8070z]

Yes I also read that the mtest is not robust enough to expose some DDR timing errors that can cause intermittent faults and non-deterministic faults. They suggested pay attention to board and PCB layout specific such as the CPO and CLK_ADJUST parameters in the DDR controllers of Freescale’s PowerQUICC and QorIQ processors. Your problem does not look like intermittent.

Freescale provides DDR validation tool

www.Freescale.com/ddrv

but it is a licensed software application that can only be purchased as part of CodeWarrior Development Suites for Networked Applications and only used inside of the CodeWarrior Development Studio for Power Architecture.

[YanjunLuo]

Thanks, finally I found it's not the DDR3's problem, when I set the P1020 to 667MHz instead of 800MHz, the DDR3 running good at 667MHz data rate. I'll focus on functions now, I'll check later why it can't run at 800MHz.

Regards,

Yanjun Luo.