Different Phase/Polarity combinations not working for eSPI on P1020RDB

[bilalwasim]

I've successfully implemented the eSPI driver on P1020RDB, but I'm currently facing a problem related to Phase/Polarity combinations. With Polarity low and Phase high, I'm able to successfully transmit data. However, if I use any other combinations, I'm unable to get the correct data transmission. I think I'm setting the registers correctly, and the configuration on the slave is also correct. Is this a hardware limitation? Can anyone point me in the correct direction.

Thanks,

Bilal

[Pavel]

Usually similar behavior happens if your SPI slave supports only this configuration: Polarity low and Phase high.

Check documentation of your SPI slave. Often SPI devices support only single Phase/Polarity combination.

For example the P1020RDB board contains the S25FL128P0XNFI00 SPI Flash;

Datasheet for this SPI Flash contains the following:

A microcontroller can use either of its two SPI modes to control Spansion SPI Flash memory devices: 

CPOL = 0, CPHA = 0 (Mode 0) 

CPOL = 1, CPHA = 1 (Mode 3)

Input data is latched in on the rising edge of SCK, and output data is available from the falling edge of SCK for both modes.

Have a great day,
Pavel Chubakov

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[bilalwasim]

The P1020RDB does support different Phase/Polarity combinations. I've verified from various sources. I'm even getting it to work at baud rates like 500 kHz, but whenever I'm using higher baud rates(~ 4000 kHz, which in fact is supported by the aardvark slave), I'm seeing problems with the data received. What, in your opinion, could be the possible reason for this. I'm just using the formula given in the manual for Baud Rate Calculation. 

[Pavel]

Usually it happens since there is signal jitter or noise at high-speed transfers. Look at sSPI timing diagrams at the Figures 14-13 and 14-14 of the P2040 Reference Manual. See also the Table 33 of the P2041 Datasheet. The P2041 eSPI requires 7ns for Master data (internal clock) input setup time. It is not simple requirement for high speed data transfers and the SPMODEx[CPx] = 1.

Usually there is no problem if SPI is configured for SPI clock toggling at the middle of data bit.

Have a great day,
Pavel Chubakov

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[bilalwasim]

Hey pavel. Just one last question. Is there something special you have to do for higher transfer length, meaning that when SPMODEx[LENx] = 15, do I have to set any other bit in any register for proper transfer. I've tried a lot of things to get this to work, but I'm still facing little issues. Any help would be appreciated.

[Pavel]

It looks like that you should check timing SPI diagram on your board.

Try to change the HO_ADJ field and provides correct data transfers.

Have a great day,
Pavel Chubakov

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