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DDR

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michaelkachalov
Contributor I

Hello,

Our team is looking at the P2020 processor and are looking to clarify a few things with respect to the DDR3 bus clock speed.

Looking at AN4261 (rev 4), Table 12 in section 6.1.2 states that the DDR3 memory bus clock speed has a range of 300 - 400 MHz. If we choose to run the DDR3 in synchronous mode, based off of note 3 (DDR data rate is the same as the platform frequency), would this imply our platform frequency must be between 300 and 400 MHz and the actual DDR data rate would be double that (600 to 800 MHz)? For example, based off of Table 18, if a 64MHz SYSCLK is used, we can choose 6:1 Platform ratio and get a 384 MHz Platform clock. The DDR3 data rate would then be 768 MHz.

If we would want to use a faster rate, we would have to use asynchronous mode. Does table 19 imply that we can bypass the 300 to 400MHz memory bus requirement and clock the controller up to 800 MHz in asynchronous mode? Thus, we can achieve a data rate up to 1600 MHz?

Thank you

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michaelkachalov
Contributor I

Thanks,

As a follow up question:

Looking at Table 12 in the same document, do the min and max DDR memory bus clock speeds apply to only the asynchronous mode of operation?

For example, lets say we want DDR3 memory. In asynchronous operation, we provide an external clock (lets say 100MHz), and according to Table 16 we can scale it 6:1 or 8:1 to provide a DDR data rate from 600MHz to 800MHz?

But, if we run in synchronous mode, our memory bus runs at half the Platform Frequency. Lets say our platform frequency is 512MHz, our memory bus will be clocked at 256MHz. This is outside the limit of what is specified in Table 12 for DDR3 memory bus clock speed.

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r8070z
NXP TechSupport
NXP TechSupport


Have a great day,

AN4261 Table 11. Processor Clocking Range provides the clocking range for the platform and DDR memory. It says that for the fastest p2020 device maximal memory clock is 400 MHz and correspondingly the maximal data rate is 800 MHz. This limit can be achieved only in asynchronous mode. Because in synchronous mode platform clock defines the DDR controller data rate. According to the Table 11 maximal platform clock is 600 MHz, i.e. in synchronous mode the maximal data rate is 600 MHz.

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michaelkachalov
Contributor I

Thanks,

As a follow up question.

Looking at Table 12 in the same document, do the min and max DDR memory bus clock speeds apply to only the asynchronous mode of operation?

For example, lets say we want DDR3 memory. In asynchronous operation, we provide an external clock (lets say 100 MHz), and according to Table 16 we can scale it 6:1 or 8:1 to provide a DDR rate from 600MHz to 800MHz?

But if we run in synchronous mode, our memory bus runs at half the Platform Frequency. Lets say our platform frequency is 512 MHz, our memory bus will be clocked at 256MHz. This is outside the limit of what is specified in Table 12 for DDR3 memory bus clock speed.

Thanks

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