Bringup P2041 hardware issues:

[woyeah]

Bringup P2041 hardware issues:

I failed to bringup a bare board no RCW word with P2041 cpu.

Following the test case:

test case1:

Power up the P2041 board with rcw src setting with hardcode word( any tye), after dessert Poreset signal, the reset_req_b pin of P2041 was always high "1",but Hreset pin of P2041 was driven to "0" level.

test case2:

Power up the P2041 board with rcw src setting with nor flash 8 bit width, after dessert Poreset signal, the reset_req_b pin of P2041 was "0" level, but Hreset pin of P2041 was driven to "0" level. the LCLK0 pin output a 6.25MHz clock, CS0 of P2041 output four valid chipset signals, We tested on P2041rdb with same setting case, the CS0 of P2041 output eight valid chipset signals.

Power up the P2041 board with rcw src setting with nor flash 16 bit width, after dessert Poreset signal, the reset_req_b pin of P2041 was "0" level, but Hreset pin of P2041 was driven to "0" level. the LCLK0 pin output a 6.25MHz clock, CS0 of P2041 output two valid chipset signals, We tested on P2041rdb with same setting case, the CS0 of P2041 output four valid chipset signals.

Power up the P2041 board with rcw src setting with SDHC card, after dessert Poreset signal, the reset_req_b pin of P2041 was "0" level, but Hreset pin of P2041 was driven to "0" level. the SDHC clk pin output a 50KHz clock, cmd of SDHC output  signals, 

We can't connect to P2041 customer board  with error message " can't stop the core of "under all these cases with codewarrior tap, 

[alexander_yakov]

Please look P2040 Reference Manual, Section 4.6.1 "Power-on reset sequence".

In this sequence, it is said that the device starts driving HRESET at step 4 and stops driving HRESET at step 14.

So, if you see HRESET is driven asserted (low) and not released, than this meas the device does not come from reset, and something happens between steps 4 and 14. Please check everything mentioned in these steps and verify everything - RCW source, RCW itself, PBL, PLL configuration, PLL input frequency, PLL-related power supplies. Also please check it TRST is asserted at least once with PORESET.

For further debugging please open a support case to Online Technical Support and attach your schematic to that case.

To enter a case to online technical support please perform the following:

1. Open www.nxp.com

2. Click on "Account" or your name in upper right corner and select "My account", enter your NXP site login/password if necessary.

3. Select "View all Support Methods" in Support section.

4. Click "Go to Tickets" in "Support Requests" section

5. The system should redirect you to this page https://nxpcommunity.force.com/community/CommunityContextPage 

6. At this page please create a new folder for support cases by clicking "Add a Folder". Typically - one folder per project.

7. When asked, enter project details - design stage, projected annual volume, end application type and application name.

8. When folder is created, please click "Add a new case" button to create support case.

Have a great day,
Alexander
TIC

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