If I don’t use the USB interface in the 3041, can I leave USBx_VDD_3P3 and USBx_VDD_1P0 pins not connected? In P4040 they are reserve with note do not connect. Can they be connected to 3.3V and 1.0V respectively? USB_VDD_1P0 must be tied to 1V or the platform voltage (based on whatever the SOC core digital power supply is). USB_VDD_3P3 can be left floating. If I don’t use USB, is it safe to leave USBx_IBIAS_REXT and USBx_VDD_1P8_DECAP unconnected? If USB is not to be used at all, keep the following USB signals floating : USB1_IBIAS_REXT, USB2_IBIAS_REXT, USB1_VDD_1P8_DECAP and USB2_VDD_1P8_DECAP, USB1_VDD_3P3, USB2_VDD_3P3.

Does P1016/P1025 come with SerDes clocks enabled? Will P1016/P1025 remain in reset if the SERDES is enabled and no SerDes reference clock is available? Yes, P1016/P1025 comes with SerDes clocks enabled. However, P1016/P1025 doesn't wait for SERDES PLL lock for it to come out of reset. For P1016/P1025, which jitter spec (tCLK_DJ, tCLK_TJ or tCLK_DJ+tCLK_TJ) should the buffer and oscillator require to meet? The input jitter at the SD_REF CLK input is specified, Buffer vendor will have to provide jitter at the output in pk-to-pk terms so that it can be compared with the Tj at SD_REF CLK input What is the relationship between RMS jitter and peak-to-peak jitter in P1016/P1025? How can I calculate the RMS jitter value from our peak-to-peak jitter value (42 ps and 86 ps)? RMS jitter is only valid for Random (Gaussian distribution) jitter. This rms value is then converted to pk-to-pk value and added to Deterministic jitter (pk-to-pk) for finding the total jitter (in pk-to-pk). For SD_REF CLK, the HW specs state the value for Total jitter (in peak to peak ps) and Deterministic jitter (in peak to peak ps). rms value for Rj can be referred from PCI Express™ Jitter and BER Revision 1.0. Converting the rms to pk-to-pk is not going to help here because the buffer datasheet states the additive phase jitter. This is measured by integrating the phase noise over the frequency band of interest. DDR. “In asynchronous mode, the memory bus clock speed must be less than or equal to the CCB clock rate which in turn must be less than the DDR PLL rate." Is this statement correct for P1025? No it is not correct. The correct statement is " In asynchronous mode, if the ratio of the DDR data rate to the CCB clock rate is greater than 3 :1 ( i.e. DDR=3:CCB=1 ), than the DDR performance monitor statistic accuracy cannot be guaranteed."

The JTAG IDCODE for P5010 is 0x0020c01d. What's the IDCODE for the P5010? Below are the JTAG IDCODES for P5010 and P5020: P5010: 0x0020_D_01D P5020: 0x0020_C_01D For P5020, COP header has COP_CHKSTP_OUT and COP_CHKSTP_IN connections. Are they actually driven by the run control device (USB TAP)? If I leave the pins appropriately terminated then I do not need to route them to an adapter cable, right? The USBtap does not use these signals at all. It's okay to leave these pins on the cop header as a NC. You do not need to route them to an adapter cable. For P5020, VDD_SENSE on COP header uses 10-Ohm to OVDD while VIO VSense on Aurora header uses 1K pull-up to OVDD. If I use the 1K Ohm then it will be okay for the USB TAP, right? Yes, this is okay for the USB TAP. They definitely use the VDD_SENSE pin, but they draw very little current, so there's almost no voltage drop. COP header has a COP_SRESET# connection on pin #11 which connects to HRESET# on the P5020. The Aurora header does not have this connection. Is it actually necessary for COP header to drive HRESET# on the P5020 device? The USB TAP does not use the /SRESET pin on the COP header at all. You don't need to route this to the COP header also. You can leave it NC.

Routing the DDR Memory Channel To help ensure the DDR interface is properly optimized, Freescale recommends routing the DDR memory channel in this specific order: 1. Data 2. Address/command/control 3. Clocks Note: The address/command, control, and data groups all have a relationship to the routed clock. Therefore, the effective clock lengths used in the system must satisfy multiple relationships. It is recommended that the designer perform simulation and construct system timing budgets to ensure that these relationships are properly satisfied. Routing DDR3 Data Signals The DDR interface data signals (MDQ[0:63], MDQS[0:8], MDM[0:8], and MECC[0:7]) are source-synchronous signals by which memory and the controller capture the data using the data strobe rather than the clock itself. When transferring data, both edges of the strobe are used to achieve the 2x data rate. An associated data strobe (DQS and DQS) and data mask (DM) comprise each data byte lane. This 11-bit signal lane relationship is crucial for routing (see Table 1). When length-matching, the critical item is the variance of the signal lengths within a given byte lane to its strobe. Length matching across all bytes lanes is also important and must meet the t DQSS parameter as specified by JEDEC. This is also commonly referred to as the write data delay window. Typically, this timing is considerably more relaxed than the timing of the individual byte lanes themselves: Table 1: Byte Lane to Data Strobe and Data Mask Mapping Data Data Strobe Data Mask Lane Number MDQ[0:7] MDQS0, MDQS0 MDM0 Lane 0 MDQ[8:15] MDQS1, !MDQS1 MDM1 Lane 1 MDQ[16:23] MDQS2, !MDQS2 MDM2 Lane 2 MDQ[24:31] MDQS3, !MDQS3 MDM3 Lane 3 MDQ[32:39] MDQS4, !MDQS4 MDM4 Lane 4 MDQ[40:47] MDQS5, !MDQS5 MDM5 Lane 5 MDQ[48:55] MDQS6, !MDQS6 MDM6 Lane 6 MDQ[56:63] MDQS7, !MDQS7 MDM7 Lane 7 MECC[0:7] MDQS8, !MDQS8 MDM8 Lane 8 DDR Signal Group Layout Recommendations Table 2 lists the layout recommendations for DDR signal groups and the benefit of following each recommendation: Table 2: DDR Signal Groups Layout Recommendations Recommendation Benefit Route each data lane adjacent to a solid ground reference for the entire route to provide the lowest inductance for the return currents Provides the optimal signal integrity of the data interface Note: This concern is especially critical in designs that target the top-end interface speed, because the data switches at 2x the applied clock When the byte lanes are routed, route signals within a byte lane on the same critical layer as they traverse the PCB motherboard to the memories Helps minimize the number of vias per trace and provides uniform signal characteristics for each signal within the data group Alternate the byte lanes on different critical layers Facilitates ease of break-out from the controller perspective, and keeps the signals within the byte group together

Can the P4040 eSPI controller address 4-byte (32-bit) addressable EEPROMs in any situation? Yes, eSPI controller addresses 4-byte addressable EEPROMs in any situation. For P4040, is it possible to boot from a 4-byte EEPROM using the on-chip ROM? No. The software in the on-chip ROM only supports 16-bit addressable or 24-bit addressable EEPROMs.

What is the integrated phase noise jitter requirement for SD_REF_CLK and SYSCLK for P2041? We don't have the integrated phase noise jitter, the SYSCLK we defined the period jitter and phase noise. For SD_REF_CLK, we follow the PCIe industrial standard spec and it defined peak-to-peak jitters. What is the PLL loop bandwidth of internal PLL in P2040 which uses 100MHz and 125MHz refclks from system? The PLL loop bandwidth of internal PLL is >= 500 KHz. The PLL bandwidth varies with many factors including ref clock rate.

For P1013/P1022, when I am using a DDR controller with a 64-bit interface with a 32-bit memory sub system, which lanes should I use? When a 64-bit DDR interface is configured in a 32-bit data bus width, lanes [0:3] (MDQ [0:31]) will be used.

For P2041, if USB1 and USB2 ports are not implemented, what to do with the unused USB ports ie tie them to ground, 3.3V or leave them unconnected? If USB is not to be used at all, keep the following USB signals floating: USB1_IBIAS_REXT, USB2_IBIAS_REXT, USB1_VDD_1P8_DECAP, USB2_VDD_1P8_DECAP, USB1_VDD_3P3 and USB2_VDD_3P3. The following signals should be pulled-down: USB1_VBUS_CLMP, USB2_VBUS_CLMP and USB_CLKIN. Also, pins USB_VDD_1P0 and USB2_VDD_1P0 must be tied to 1V or the platform voltage (whatever is the SOC core digital power supply) If USB_VDD_3P3 must be connected to 3.3V, will the power sequence be same as other 3.3V (OVDD) (no special power sequence for USB_VDD_3P3)? Even if PHY is not used, USB_VDD_1P0 must be tied to 1V or the platform voltage (whatever is the SOC core digital power supply), other pins can be left floating: USB1_IBIAS_REXT, USB2_IBIAS_REXT, USB1_VDD_1P8_DECAP and USB2_VDD_1P8_DECAP, USB1_VDD_3P3, USB2_VDD_3P3. If signals USB_VDD_3P3 and USB_VDD_1P8 are left floating, there is no need to take of power sequencing on these pins, only USB_VDD_1P0 must be a part of standard power sequencing requirements. If signals USB_VDD_3P3 and USB_VDD_1P8 are used (i.e. not left floating), power sequencing is to be done as under: Follow a minimum ramp time of 350us on USB_VDD_3P3(most regulators would give a 350us ramp time) and standard power sequencing on USB_VDD_1P0,USB_VDD_3P3. USB_VDD_1P8_DECAP would only have 1uF capacitor and is automatically tolerant of sequencing on rest of the supplies are sequenced properly. Also based on silicon validation: There is no power down sequencing to be followed on the PHY. There requirements were added as a backup strategy in case the new regulator in the IP had a problem. We have tested this regulator, so no power down sequencing requirements is needed. There is no need to supply any power to USB_VDD_1P8_DECAP, as the circuit is working fine.

When setting the ABSWP bit (in LBCR) in P1020, are the address bytes swapped or just mirrored? Also, can you confirm that the LBCR [ABSWP] affect every device (chip select) being used by the local bus except for the NAND Flash? By setting ABSWP bit (i.e. ABSWP=1), if address=0x12345678. Then LAD [0:15] = 0x7856 and LA[16:31]=0x5678. LBCR [ABSWP] affect every device (chip select) being used by the local bus except for the NAND Flash What is NAND Flash controller speed and size for P1011? AeLBC can work at 83 MHz. At minimum twc, it can be equal to 2 LCLK i.e. half the frequency of LCLK. The maximum page size supported by eLBC is 2K. If I use one mck to drive all 5 ddr3-chips in P1011, can I use the leveling function? Also, which topology do you recommend for this? Yes, writing leveling function should be used to compensate the additional flight time skew delay between different chips introduced by fly-by topology. However, we do not recommend routing the clock in fly-by topology while address, command and control signals routed by other topology. For more detail of JEDEC DDR3 routing topology, please visit [www.JEDEC.org]. Is a 32-bit data interface the only way to control whether or not ABSWP applies (i.e. ABSWP affects 8 and 16-bit data interfaces but does not affect 32-bit data interfaces)? ABSWP also affects 32-bit interface and it is not advisable to set ABSWP for 32 bit interface as only 16 LSB address gets visible on LAD[0:15] and zeroes are output on the LAD[16:31].

For P4040, does DDRCLK and PCIe (SerDes) ref clock support a spread spectrum reference? DDRCLK and PCIe (SerDes) ref clock support spread spectrum. Please note that since SGMII doesn't support spread spectrum, if SGMII is used on any SERDES lane, spread spectrum should not be applied to SERDES REF clock. What are the DDRCLK and PCIe (SerDes) reference clock spread spectrum parameters for P4040?  DDRCLK and PCIe (SerDes) reference clock are designed to work with a spread spectrum clock (+0 to –0.5% spreading at 30–33 KHz rate is allowed), assuming both ends have same reference clock. For better results, a source without significant unintended modulation should be used.

For a single eTSEC, I am wiring two external devices via both its parallel interface and SGMII I/F at same time, and either of interfaces actually used will be determined by POR configuration pins. Is this usage possible? Yes. Please ensure that you all the related POR config pins are properly driven.

The on-chip ROM code does not set up any local access windows (LAWs). Access to the CCSR address space or the L2 cache does not require a LAW. It is the user’s responsibility to set up a LAW through a control word address/data pair for the desired target address and execution starting address (which is typically in either DDR or local bus memory space). Required Configurations for SD Card/MMC Booting The configuration settings required to boot from an SD card/MMC are as follows: Ensure that cfg_rom_loc[0:3] (Boot_Rom_Loc) are driven with a value of 0b0111. Only one core can be in booting mode. If your device has multiple cores, all other cores must be in a boot hold-off mode. The CPU boot configuration input, cfg_cpux_boot, should be 0, where x is from 1 to n (n = the number of cores). Booting from the eSDHC interface can occur from different SD card slots if multiple SD card slots are designed on the board. In this case, ensure the appropriate SD card/MMC is selected For example, on the P5010 board, bit 7 of the SW8 is used to select which SD/MMC slot is used. If SW8[7] = 1, an SD card/MMC must be put to the external SD card/MMC slot (J1). TIP The polarity of the SDHC_CD signal should be active-low.  Required Configurations for EEPROM Booting The configuration settings required to boot from an EEPROM are as follows: Ensure that cfg_rom_loc[0:3] (Boot_Rom_Loc) are driven with a value of 0b0110. Only one core can be in booting mode. If your device has multiple cores, all other cores must be in a boot hold-off mode. The CPU boot configuration input, cfg_cpux_boot, should be 0, where x is from 1 to n (n = the number of cores). The eSPI chip select 0 (SPI_CS[0]) must be connected to the EEPROM that is used for booting. No other chip select can be used for booting. This is because during booting, the eSPI controller is configured to operate in master mode. Booting from the eSPI interface only works with SPI_CS[0].

For P1020, having a target to achieve the max frequency on local bus what are the requirements on the clock that have to be met? You should pay close attention to the platform clock PLL filtering to minimize jitter. In general keep the bus as short as possible and the trace lengths matched for timing to meet the mentioned Hardware spec requirements.

Can you explain me the detailed description of bit functionality in field Error Capture ECC (ECE) for P1012/P1021? Following is the correct description of bits in Error Capture ECC (ECE): 0:7 -8-bit ECC for the 16 bits in beats 0 & 4 in 16-bit bus mode; should be ignored for 32-bit and 64-bit mode 8:15 -8-bit ECC for the 16 bits in beats 1 & 5 in 16-bit bus mode; should be ignored for 32-bit and 64-bit bus mode 16:23 -8-bit ECC for the 16 bits in beats 2 & 6 in 16-bit bus mode; for the 32 bits in beats 0 & 2 & 4 & 6 in 32-bit bus mode; should be ignored for 64-bit mode 24:31 -8-bit ECC for the 16 bits in beats 3 & 7 in 16-bit bus mode; for the 32 bits in beats 1 & 3 & 5 & 7 in 32-bit bus mode; should be used for every beat in 64-bit mode Bits 0:15 bits are not reserved in P1012/P1021. How can I support GPCM based Local Bus (like a boot NOR FLASH) on memory controller part with all 4 TDM ports in use due to pin mux restrictions in P1012/P1021? You can boot from GPCM as the pins as configured as eLBC signals by default. But if you intent to use them simultaneously, you cannot. You'll have to use some isolation logic on board to switch from one protocol to other. Is there a possibility to support higher density of DDR2/3 with P1021 at a later stage in design? For example JEDEC specifies 8Gbits density for DDR3. Yes, there is a possibility to support higher density devices in P1021. For a single discrete memory (single chip select), the max memory size that can be supported is 4GB. With a single chip-select we can support max of 4 GB, so with two chip-select we can support a maximum of 8 GB with two discrete devices. HW spec.

How can I ensure that Ethernet flow control is turned on through the register setting in P4040? Please try the below steps to enable Ethernet flow control: 1) Set MACCFG1[Rx_Flow] && MACCFG1[Tx_Flow] to 1 2) Set RCTRL[LFC] to 1. Setting the flow control bits Rx_Flow and Tx_Flow means that the MAC can detect and act on PAUSE flow control frames, receive and transmit respectively. There are two ways you can confirm or see them in action: 1) Software sending a PAUSE frame through TCTRL[TFC_PAUSE] 2) Changing some hidden FIFO threshold registers, such that the FIFO is about to overflow and that triggers eTSEC logic to send a PAUSE.

Do we have an internal pull up on LA20 pin in P1015E? According to hardware spec for P1015/P1024, LA20 pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the processor is in the reset state. This pull-up is designed such that it can be overpowered by an external 4.7-kΩ pull-down resistor. Assuming that I did not include a pull up or pull down and assuming no device was asserting LA20--what state do we sample at POR? If LA20 is left floating at POR, would one read the SVR for P1015E (80ED0211) OR P1011E (80ED0011)? According to hardware spec for P1015/P1024, LA20 pin "must be pulled down with a 4.7K resistor". So the default in case that a design doesn't include an external pull (as required by the spec) is for it to sample as a '1'. Leaving the pin NC (floating) at POR is effectively an out of spec configuration.

If I select a SerDes Mux config using a PCIe controller on 2 lanes, is it possible to use just one lane, although it is configured to two lanes PCIe? Do you have any advice for such configuration? A13. Yes, it is possible to use just one lane while selecting SerDes Mux config using a PCIe controller. From the P2040 SERDES options ECI will be setting PCIe2 to use lanes E & F. If you have them pinned out to x2 connector then it will automatically train down to x1 if a x1 device is inserted. If you don't want to use lane F then power lane F down during reset and set SRDSPCCR0[PEX2_CFG] to x1. What is the function of TRSTDIR bit found in Table 3-26/B1GCRA1–B1GCRJ1 Field Descriptions B1GCRA1 [TRSTDIR] in P2041 RM? It controls Lynx Tx lane reset function for multi-lane protocols. For multi-lane protocols where the lanes are from left to right (PEX, XAUI), it should be set to 1 while for protocols where the lanes are from right to left (SRIO, Aurora), it should be set to 0. For single-lane protocols (SGMII, SATA) it doesn’t matter. It is paired with BnGCRm0[1STLANE], which determines the master source clock lane for a multi-lane protocol (must always be =1 for nominal lane 0 for the protocol, e.g. lane A for PEX on lanes A-D, and =0 for all other lanes).

If I don’t use the USB interface in the 4080, can I leave USBx_VDD_3P3 and USBx_VDD_1P0 pins not connected? In P4040 they are reserve with note do not connect. Can they be connected to 3.3V and 1.0V respectively? USB_VDD_1P0 must be tied to 1V or the platform voltage (based on whatever the SOC core digital power supply is). USB_VDD_3P3 can be left floating. If I don’t use USB, is it safe to leave USBx_IBIAS_REXT and USBx_VDD_1P8_DECAP unconnected? If USB is not to be used at all, keep the following USB signals floating : USB1_IBIAS_REXT, USB2_IBIAS_REXT, USB1_VDD_1P8_DECAP and USB2_VDD_1P8_DECAP, USB1_VDD_3P3, USB2_VDD_3P3.

If unused, how do I terminate following pins in P1011/P1020: SDHC_DATA[0:2], SDHC_DAT3, SPI_CS[0:3]/SDHC_DAT[4:7] and SPI_CS0_B/SDHC_DATA4? All the 3 pins SDHC_DATA[0:2], SDHC_DAT3 and SPI_CS[0:3]/SDHC_DAT[4:7] should be don't care if not used. Please leave SPI_CS0_B.SDHC_DATA4 as floating when not used. I have designed my P1011 board based on the older hardware spec, and found that AVDD_CORE0 and AVDD_CORE1 were swapped in newer hardware spec. At this time, it is difficult to cut the pattern for the current AVDD_CORE1. So 1.0V power applied to AVDD_CORE1 though core 1 is not used. Does this cause any problem? If AVDD_CORE1 is powered in single core device, there'll be no problem. But if AVDD_CORE0 is not powered in single core device, the device may not boot up. How should I handle pin W26,F16 pins in P1020? Just let them "NC", or need connect them to AVdd? If AVDD_CORE1 is not powered up i.e. connected to 1.0V, the single core p101x device cannot be boot up. Please implement the AVDD circuit at this stage.

Routing the DDR Memory Channel To help ensure the DDR interface is properly optimized, Freescale recommends routing the DDR memory channel in this specific order: 1. Data 2. Address/command/control 3. Clocks Note: The address/command, control, and data groups all have a relationship to the routed clock. Therefore, the effective clock lengths used in the system must satisfy multiple relationships. It is recommended that the designer perform simulation and construct system timing budgets to ensure that these relationships are properly satisfied. Routing DDR3 Data Signals The DDR interface data signals (MDQ[0:63], MDQS[0:8], MDM[0:8], and MECC[0:7]) are source-synchronous signals by which memory and the controller capture the data using the data strobe rather than the clock itself. When transferring data, both edges of the strobe are used to achieve the 2x data rate. An associated data strobe (DQS and DQS) and data mask (DM) comprise each data byte lane. This 11-bit signal lane relationship is crucial for routing (see Table 1). When length-matching, the critical item is the variance of the signal lengths within a given byte lane to its strobe. Length matching across all bytes lanes is also important and must meet the t DQSS parameter as specified by JEDEC. This is also commonly referred to as the write data delay window. Typically, this timing is considerably more relaxed than the timing of the individual byte lanes themselves: Table 1: Byte Lane to Data Strobe and Data Mask Mapping Data Data Strobe Data Mask Lane Number MDQ[0:7] MDQS0, MDQS0 MDM0 Lane 0 MDQ[8:15] MDQS1, !MDQS1 MDM1 Lane 1 MDQ[16:23] MDQS2, !MDQS2 MDM2 Lane 2 MDQ[24:31] MDQS3, !MDQS3 MDM3 Lane 3 MDQ[32:39] MDQS4, !MDQS4 MDM4 Lane 4 MDQ[40:47] MDQS5, !MDQS5 MDM5 Lane 5 MDQ[48:55] MDQS6, !MDQS6 MDM6 Lane 6 MDQ[56:63] MDQS7, !MDQS7 MDM7 Lane 7 MECC[0:7] MDQS8, !MDQS8 MDM8 Lane 8 DDR Signal Group Layout Recommendations Table 2 lists the layout recommendations for DDR signal groups and the benefit of following each recommendation: Table 2: DDR Signal Groups Layout Recommendations Recommendation Benefit Route each data lane adjacent to a solid ground reference for the entire route to provide the lowest inductance for the return currents Provides the optimal signal integrity of the data interface Note: This concern is especially critical in designs that target the top-end interface speed, because the data switches at 2x the applied clock When the byte lanes are routed, route signals within a byte lane on the same critical layer as they traverse the PCB motherboard to the memories Helps minimize the number of vias per trace and provides uniform signal characteristics for each signal within the data group Alternate the byte lanes on different critical layers Facilitates ease of break-out from the controller perspective, and keeps the signals within the byte group together