Please confirm that a PCIe lane on the P1023 can be enabled after POR (configured off in h/w but turned on in s/w). If so how this would be implemented?
It is possible to control PCIe Lane turned on through s/w. You can control this through SRDSCR2 [0:7]. Through this control you can power -up or power- down individual lanes separately
What is the difference between two strap options for PCIe ports - 0b00 or 0b11?
In terms of PCIe, options 0b00 and 0b11 are redundant, but in terms of SGMII, they are different
0b00 - 2 lanes are for PCIe; the remaining 2 lanes are powered down 0b11 - 2 lanes are for PCIe; the remaining 2 lanes are for SGMII
0b01 - 3 lanes are for PCIe; the remaining 1 lane is powered down 0b10 - 3 lanes are for PCIe; the remaining 1 lane is for SGMII
When SGMII is not used, the corresponding lane(s) should be powered down to save power.
