Booting P1020/P1011 from On-Chip ROM (eSDHC or eSPI)

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The on-chip ROM code does not set up any local access windows (LAWs). Access to the CCSR address space or the L2 cache does not require a LAW. It is the user’s responsibility to set up a LAW through a control word address/data pair for the desired target address and execution starting address (which is typically in either DDR or local bus memory space).

Required Configurations for SD Card/MMC Booting

The configuration settings required to boot from an SD card/MMC are as follows:

• Ensure that cfg_rom_loc[0:3] (Boot_Rom_Loc) are driven with a value of 0b0111.
• Only one core can be in booting mode. If your device has multiple cores, all other cores must be in a boot hold-off mode. The CPU boot configuration input, cfg_cpux_boot, should be 0, where x is from 1 to n (n = the number of cores).
• Booting from the eSDHC interface can occur from different SD card slots if multiple SD card slots are designed on the board. In this case, ensure the appropriate SD card/MMC is selected For example, on the P1020 board, bit 7 of the SW8 is used to select which SD/MMC slot is used. If SW8[7] = 1, an SD card/MMC must be put to the external SD card/MMC slot (J1).

TIP The polarity of the SDHC_CD signal should be active-low.

Required Configurations for EEPROM Booting

The configuration settings required to boot from an EEPROM are as follows:

• Ensure that cfg_rom_loc[0:3] (Boot_Rom_Loc) are driven with a value of 0b0110.
• Only one core can be in booting mode. If your device has multiple cores, all other cores must be in a boot hold-off mode. The CPU boot configuration input, cfg_cpux_boot, should be 0, where x is from 1 to n (n = the number of cores).
• The eSPI chip select 0 (SPI_CS[0]) must be connected to the EEPROM that is used for booting. No other chip select can be used for booting. This is because during booting, the eSPI controller is configured to operate in master mode. Booting from the eSPI interface only works with SPI_CS[0].