sgtl5000 datasheet ambiguity

[AlexLL]

Hello,

I have a question about the following document:

Document Number: SGTL5000 Rev. 7, 1/2022

The Table 18, page 32 describes bit fields of CHIP_CLK_CTRL register (addr=0x4).

The "definition" column of this table says that MCLK_FREQ field depends upon some value called "Fs" which is not defined anywhere in the document.

I guess (but not sure, please confirm) that "Fs"=SYS_FS when RATE_MODE=0.

My question is: what is "Fs" when the RATE_MODE field is NOT set to 0?

I set RATE_MODE=2 but do not see any changes in the output waveform.

How one can make use of RATE_MODE > 0 feature?

Thanks

[JorgeCas]

Hello,

For PLL mode, the SYS_FS / RATE_MODE = Fs equation is only true with SCLKFREQ
setting of 64Fs (SCLKFREQ=0).

Best regards.

[AlexLL]

Thanks. I've tried this settings but unfortunately it did not work.

BTW datasheet says (pg. 1 and pg.10) that SYS_MCLK clock can take clock from 8MHz to 27MHz ONLY. In your proposed settings it is 4.096MHz. Can that be the reason for the problem?

I saw that the range issue was already addressed on this forum. See for ex. 

https://community.nxp.com/t5/Other-NXP-Products/SGTL5000-minimum-SYS-MCLK-frequency/m-p/1393679/high...

Meanwhile datasheet says that Fs=8000Hz is achievable. 

So the question remains: HOW?

Regards

[AlexLL]

Does that apply to Slave mode as well?

[JorgeCas]

Hello,

Yes, you need to configure it when the SGTL5000 is in slave mode.

In slave mode, it receives the BCLK and LRCLK from the master but, SYS_FS and MCLK_FREQ fields in CHIP_CLK_CTRL needs to be set correctly to ensure internal timing and routing.

Best regards.

[AlexLL]

May I ask you to please clarify.

Suppose I'd like to set up codec to 8000Hz sample rate.

In Slave mode I set SYS_FS=0 (32kHz) and RATE_MODE=2 (Fs=SYS_RATE/4=32kHz/4=8000Hz).

If I choose MCLK_FREQ=2 (512*Fs), should I provide 32kHz*512 = 16.384MHz  or 8kHz*512=4.096MHz as master clock?

Same question about  SCLKFREQ. If I choose SCLKFREQ=0 (64Fs), should I provide bit clock 2.048MHz or 512kHz?

Thanks

[JorgeCas]

Hello,

In synchronous mode, the the frequency of the SCLK bit clock just directly
depends on the frequency of the SYS_MCLK input clock. It can be calculated as
follows depending on the MCLK_FREQ bit settings.

SCLK = SYS_MCLK/8 for MCLK_FREQ = 0 (256Fs)
SCLK = SYS_MCLK/12 for MCLK_FREQ = 1 (384Fs)
SCLK = SYS_MCLK/16 for MCLK_FREQ = 2 (512Fs)

Then, the Fs frequency can be calculated as SCLK/32 or SCLK/64 depending on the
SCLKFREQ bit setting.

Best regards.

[AlexLL]

Hello, I understand what you say - it is excerpt from your datasheet and there is no need to repeat it here. I have read datasheet and I find it ambiguous. So to simplify the matter please answer my questions instead. I paste them here again for your convenience:

Suppose I'd like to set up codec to 8000Hz sample rate when in synchronous (slave) mode.

I set SYS_FS=0 (32kHz) and RATE_MODE=2 (Fs=SYS_RATE/4=32kHz/4=8000Hz).

(1)  If I choose MCLK_FREQ=2 setting (512*Fs), should I provide (a) 32kHz*512 = 16.384MHz  or  (b) 8kHz*512=4.096MHz as master clock?

(2) If I choose SCLKFREQ=0 (64Fs) setting, should I provide bit clock (a) 2.048MHz or (b) 512kHz?

I hope that if you know what you're trying to say it won't be difficult for you to answer something like for ex. (1)a and (2)b. If you believe that none of the options (a) nor (b) are correct then please advise about the correct values for my example.

Your datasheet is ambiguous hence are my questions!

Thanks for your help

[JorgeCas]

Hello,

I apologize for the delay.

1.

If you need to set up the CODEC to 8000Hz sample rate in synchronous slave mode, the correct configuration is 8kHz*512=4.096MHz because the rate mode affects the sample rate and not the not the raw SYS_FS.

2.

In the case of the SCLK, since rate mode divides SYS_FS by 4, the bit clock must be 512 kHz.

Best regards.

[AlexLL]

Thanks. I've tried this settings but unfortunately it did not work.

BTW datasheet says (pg. 1 and pg.10) that SYS_MCLK clock can take clock from 8MHz to 27MHz ONLY. In your proposed settings it is 4.096MHz. Can that be the reason for the problem?

I saw that the range issue was already addressed on this forum. See for ex. 

https://community.nxp.com/t5/Other-NXP-Products/SGTL5000-minimum-SYS-MCLK-frequency/m-p/1393679/high...

Meanwhile datasheet says that Fs=8000Hz is achievable. 

So the question remains: HOW?

Regards

[JorgeCas]

Hello,

You are right, the minimum working frequency is 8MHz.

If you are under the working frequency range, it will use an internal PLL to derive the audio clocks. MCLK_FREQ and SCLKFREQ are based on the effective Fs But, the actual SYS_MCLK input must still be greater than 8MHz, so you provide a clock based on the unmodified SYS_FS.

You can use this configuration as example in the application note:

I2S DSP Mode

This document shows how to use RATE_MODE to derive 8 kHz from a higher SYS_FS like 48 kHz.

Best regards.

[AlexLL]

Hello, are you trying to say that Fs=8000Hz is only possible when I2S is in "DSP mode"?
Also what do you mean under "effective Fs"?
Regards

[AlexLL]

On Aug 29th I've got email notification about new reply on the topic. However I do not see it here. Please help