mpc8313uboot nor

leilei987 · ‎04-15-2021

hi
i project use mpc8313
uboot printf

U-Boot 1.1.6-gacb2702c-dirty (Apr 15 2021 - 14:24:48) MPC83XX
Board LF7511
CPU: MPC8313, Rev: 21 at 333.333 MHz
INFO: Initializing IOMEM for regset 0
INFO: reset phy for M88E1340 card
DRAM: 256 MB
FLASH: 64 MB
NAND: 256 MB
Using default environment
In: serial
Out: serial
Err: serial
Net: ....TSEC1: PHY is Marvell 88E1340 (1410dc0)
....TSEC2: PHY is Marvell 88E1340 (1410dc0)
TSEC1 [PRIME], TSEC2
Boot in 3 seconds
=> ......

#define CFG_BR0_BASE 0xe8000000 /* u-boot presumes it is the address needed to */
#define CFG_FLASH_CFI /* use the Common Flash Interface */
#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CFG_FLASH_BASE CFG_BR0_BASE /* start of FLASH */
#define CFG_FLASH_SIZE 64 /* flash size in MB */
#define CFG_FLASH_EMPTY_INFO /* display empty sectors */
#define CFG_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
#define CFG_BR0_PRELIM 0xe8001001
#define CFG_OR0_PRELIM 0xfc006ff7
#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */
#define CFG_LBLAWAR0_PRELIM 0x80000019 /* 64 MB window size */
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
#define CFG_MAX_FLASH_SECT 512 /* sectors per device */

The code above is my br0 or0 br1 or1 config
cs0 is link S29GL512T nor flash
cs1 is link MT29F2G08ABAEA nand falsh

I use bdi2000 load uboot.bin to ddr
uart input as follow cmd :

erase e8000000 +0x100000

tftp 0x100000 u-boot.bin

cp.b 0x100000 0xe8000000 $filesize

cmp.b 0x100000 0xe8000000 $filesize

burn the uboot.bin to norflash 0 space

i want to uboot self-starting nor flash because old version is self-starting nand flash

first
the hardware modified:
1 CFG_RESET_SOURCE[0:3]=TSEC2_TXD[3:0] 0000
2 cs0 is link nor faslh

second

uboot code modyfi front
CFG_HRCW_HIGH hrcw config

BMS is 0b ROMLOC 011b RLEXT 00b

but uart no printf? ? ?wait 10s??The serial port is not printed out either
how about ,
rcw br or？
Is there anything else that needs to be revised and confirmed

yipingwang · ‎04-19-2021

Please compile u-boot with configs/MPC8313ERDB_33_defconfig or MPC8313ERDB_66_defconfig.

Please modify your u-boot configuration based on include/configs/MPC8313ERDB.h.

View solution in original post

yipingwang · ‎04-16-2021

Did you do your porting based on MPC8313ERDB?

Did you modify include/configs/MPC8313ERDB.h? Would you please provide your header file in include/configs/?

Please check whether SYS_TEXT_BASE is defined correctly, please refer to the following.

#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xe8000000
#endif

leilei987 · ‎04-17-2021

hi

YIPING

i use uboot version is 1.1.6

this version have a little old

only in my private compile Script have:

ifndef TEXT_BASE
TEXT_BASE = 0x1000000
endif

and private boards .h as follow

/*

* Copyright (C) Freescale Semiconductor, Inc. 2006.

*

* See file CREDITS for list of people who contributed to this

* project.

*

* This program is free software; you can redistribute it and/or

* modify it under the terms of the GNU General Public License as

* published by the Free Software Foundation; either version 2 of

* the License, or (at your option) any later version.

*

* This program is distributed in the hope that it will be useful,

* but WITHOUT ANY WARRANTY; without even the implied warranty of

* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

* GNU General Public License for more details.

*

* You should have received a copy of the GNU General Public License

* along with this program; if not, write to the Free Software

* Foundation, Inc., 59 Temple Place, Suite 330, Boston,

* MA 02111-1307 USA

*

* History

* 20061201: Wilson Lo (Wilson.Lo@freescale.com)

* Initialized

*

* 20061210: Tanya Jiang (tanya.jiang@freescale.com)

* Code Cleanup

*

*/

#ifndef __CONFIG_H

#define __CONFIG_H

#undef DEBUG

#ifdef CONFIG_TEST

#warning WARNING WARNING: TEST CONFIGURATION ENABLED

#endif

#define CONFIG_JFFS2_SUMMARY

//#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS

/*

* High Level Configuration Options

*/

#define CONFIG_E300 1

#define CONFIG_MPC83XX 1

#define CONFIG_MPC8313 1

#define CONFIG_S8313 1

#if 0

#define CONFIG_83XX_CLKIN 33333333 /* in Hz */

#define CONFIG_SYS_CLK_FREQ 33333333

#define CONFIG_83XX_PCICLK 33333333

#endif

#define CONFIG_83XX_CLKIN 33333333 /* in Hz */

#define CONFIG_SYS_CLK_FREQ 33333333

#define CONFIG_83XX_PCICLK 33333333

#define CFG_SCCR ( SCCR_RES \

| SCCR_TSEC1CM_1\

| SCCR_TSEC1ON\

| SCCR_TSEC2ON\

| SCCR_ENCCM_3\

| SCCR_USBCM_3\

| SCCR_PCICM)

#define CONFIG_BOARD_EARLY_INIT_F

#undef CONFIG_BOARD_EARLY_INIT_F

#define CONFIG_BOARD_EARLY_INIT_R

#undef CONFIG_BOARD_EARLY_INIT_R

#define CFG_IMMR 0xE0000000

#define CFG_SPI_MODE (CFG_IMMR+0x20)

#define CFG_SPIE (CFG_IMMR+0x24)

#define CFG_SPIM (CFG_IMMR+0x28)

#define CFG_SPICOM (CFG_IMMR+0x2C)

#define CFG_SPITD (CFG_IMMR+0x30)

#define CFG_SPIRD (CFG_IMMR+0x34)

/* used by memory cmd */

#define CFG_ALT_MEMTEST /* use slow test */

#define CFG_MEMTEST_START ( 1 * 1024 * 1024)

#define CFG_MEMTEST_END ( 16 * 1024 * 1024)

/*

* DDR Setup

*/

#undef CONFIG_SPD_EEPROM

#define CFG_DDR_BASE 0x00000000

#define CFG_SDRAM_BASE CFG_DDR_BASE

#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE

#undef CONFIG_DDR_2T_TIMING

#ifndef CSCONFIG_BA_2

# define CSCONFIG_BA_2 0

#endif

#ifndef CSCONFIG_BA_3

# define CSCONFIG_BA_3 0x4000

#endif

#define CFG_DDR_SIZE 256 /* MB */

#define CFG_DDR_CONFIG ( CSCONFIG_EN | CSCONFIG_AP | CSCONFIG_ODT_RD_1 | CSCONFIG_ODT_WR_1 \

| CSCONFIG_BA_3 \

| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 )

#define CFG_DDRCDR ( DDRCDR_EN \

| DDRCDR_PZ_NOMZ \

| DDRCDR_NZ_NOMZ \

| DDRCDR_M_ODR )

#define CFG_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05

#define CFG_DDR_TIMING_3 0x00000000

#define CFG_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \

| ( 0 << TIMING_CFG0_WRT_SHIFT ) \

| ( 0 << TIMING_CFG0_RRT_SHIFT ) \

| ( 0 << TIMING_CFG0_WWT_SHIFT ) \

| ( 3 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \

| ( 3 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \

| (10 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \

| ( 3 << TIMING_CFG0_MRS_CYC_SHIFT ) )

#define CFG_DDR_TIMING_1 ( ( 6 << TIMING_CFG1_PRETOACT_SHIFT ) \

| ( 0 << TIMING_CFG1_ACTTOPRE_SHIFT ) \

| ( 6 << TIMING_CFG1_ACTTORW_SHIFT ) \

| ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \

| (15 << TIMING_CFG1_REFREC_SHIFT ) \

| ( 7 << TIMING_CFG1_WRREC_SHIFT ) \

| ( 5 << TIMING_CFG1_ACTTOACT_SHIFT ) \

| ( 4 << TIMING_CFG1_WRTORD_SHIFT ) )

#define CFG_DDR_TIMING_2 ( ( 0 << TIMING_CFG2_ADD_LAT_SHIFT ) \

| (31 << TIMING_CFG2_CPO_SHIFT ) \

| ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \

| ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \

| ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \

| ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \

| (10 << TIMING_CFG2_FOUR_ACT_SHIFT) )

#define CFG_DDR_INTERVAL ( ( 800 << SDRAM_INTERVAL_REFINT_SHIFT ) \

| ( 100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )

#if defined(CONFIG_DDR_2T_TIMING)

# define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \

| 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \

| SDRAM_CFG_2T_EN \

| SDRAM_CFG_DBW_32 )

#else

# define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \

| 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \

| SDRAM_CFG_DBW_32 )

#endif

#define CFG_SDRAM_CFG2 0x00601000;

#define CFG_DDR_MODE ( ( 0x4440 << SDRAM_MODE_ESD_SHIFT ) \

| ( 0x0232 << SDRAM_MODE_SD_SHIFT ) )

#define CFG_DDR_MODE_2 0x8000C000;

/*

* Before the NAND stage 0 boot loader relocates U-BOOT

* RAM is tested - but only a small amount since cache is turned off

*/

#define CONFIG_NAND_DDR_TEST_START0 ( 0 * 1024 * 1024 )

#define CONFIG_NAND_DDR_TEST_END0 ( 2 * 1024 * 1024 )

#define CONFIG_NAND_DDR_TEST_START1 (( CFG_DDR_SIZE - 2 ) * 1024 * 1024)

#define CONFIG_NAND_DDR_TEST_END1 (( CFG_DDR_SIZE ) * 1024 * 1024)

#define CONFIG_NAND_DDR_TEST_LIST { \

CONFIG_NAND_DDR_TEST_START0, CONFIG_NAND_DDR_TEST_END0, \

CONFIG_NAND_DDR_TEST_START1, CONFIG_NAND_DDR_TEST_END1 \

}

/*

* Once U-BOOT is loaded it can test RAM, however it must avoid certain address

* ranges ....

*/

#define CONFIG_U_BOOT_DDR_TEST_START0 ( 2 * 1024 * 1024)

#define CONFIG_U_BOOT_DDR_TEST_END0 ((CFG_DDR_SIZE-2) * 1024 * 1024)

#define CONFIG_U_BOOT_DDR_TEST_LIST { \

CONFIG_U_BOOT_DDR_TEST_START0, CONFIG_U_BOOT_DDR_TEST_END0 \

}

/*

* NO FLASH

*/

#if 0

#define CFG_NO_FLASH

#endif

#define ADD_FLASH_CMD (0)

#define CFG_INIT_RAM_LOCK 1

#if 1

#define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */

#endif

#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/

#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */

#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)

#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET

/*

* Monitor

*/

#define CFG_MONITOR_BASE TEXT_BASE /* ((CFG_DDR_SIZE-1) * 0x100000) */

#define CFG_MONITOR_LEN ( 384 * 1024) /* Reserved for Mon */

#define CFG_MALLOC_LEN ( 512 * 1024) /* Reserved for malloc */

//#define CFG_GBL_DATA_SIZE ( 128 * 1024) /* Global data */

#if 0

#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) && !defined(CONFIG_NAND_U_BOOT)

#define CFG_RAMBOOT

#else

#undef CFG_RAMBOOT

#endif

/*

* This is a special case: the startup code maps LAW1 based on

* the value of CFG_FLASH_BASE and CFG_FLASH_SIZE.

*

* This allows us to fool the system into thinking we are mapped

* when we are not ( FCM failed )

*/

#if 0

#define CFG_FLASH_BASE CFG_MONITOR_BASE

#define CFG_FLASH_SIZE CFG_MONITOR_LEN

#endif

/*

* Local Bus LCRR and LBCR regs (0 is boot, 1..6)

*/

#define CFG_LCRR LCRR_EADC_1 | LCRR_CLKDIV_4

#define CFG_LBC_LBCR (0x00040000 | (0xFF << LBCR_BMT_SHIFT) | 0xF)

#define CFG_LBC_MRTPR 0x20000000

/* Default values to make it easy to add/modify CS's for debugging */

#define CFG_BR_DEFAULT 0x00000801 /* 8b GPCM */

#define CFG_BR_DEFAULT_16 0x00001001 /* 16b GPCM */

#define CFG_OR_DEFAULT 0xFFFF8104 /* 32k UPM */

#define CFG_OR_DEFAULT_1M 0xFFF00104 /* 1m UPM */

#define CFG_LBLAWAR_DEFAULT 0x8000000E /* 32k */

#define CFG_LBLAWAR_DEFAULT_1M 0x80000013 /* 1m */

/* CFG_BRX_BASE needed by s8313.c */

#ifdef CONFIG_NAND_SPL

# define CFG_NAND_BASE 0xfff00000 /* not what you think! */

/* load address for stage0 code, 0xfff00000 based*/

/* on BM bit ( 0x0 or 0xfff... ) */

#else

#if 0

/* local bus CS 0 - NAND flash */

# define CFG_BR0_BASE 0xe8000000 /* u-b

oot presumes it is the address needed to */

/* access the chip ( ale ... ) */

# define CFG_NAND_BASE CFG_BR0_BASE /* value used by u-boot to access chip */

# define CFG_LBLAWBAR0_PRELIM CFG_BR0_BASE

# define CFG_LBLAWAR0_PRELIM 0x8000000E

# define CFG_BR0_PRELIM ( CFG_BR0_BASE | (2<<BR_DECC_SHIFT) | BR_PS_8 | BR_MS_FCM | BR_V )

#endif

#define CFG_BR0_BASE 0xe8000000 /* u-boot presumes it is the address needed to */

#define CFG_FLASH_CFI /* use the Common Flash Interface */

#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */

#define CFG_FLASH_BASE CFG_BR0_BASE /* start of FLASH */

#define CFG_FLASH_SIZE 64 /* flash size in MB */

#define CFG_FLASH_EMPTY_INFO /* display empty sectors */

#define CFG_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */

#define CFG_BR0_PRELIM 0xe8001001

#if 0

#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \

(2 << BR_PS_SHIFT) | /* 16 bit port size */ \

BR_V) /* valid */

#define CFG_FLASH_OR_PRELIM ( 0xFF000000 /* 16 MByte */ \

| OR_GPCM_XACS \

| OR_GPCM_SCY_9 \

| OR_GPCM_EHTR \

| OR_GPCM_EAD )

/* 0xFF006FF7TODO SLOW 16 MB flash size */

#define CFG_MAX_FLASH_SECT 512 /* sectors per device */

#endif

#define CFG_OR0_PRELIM 0xfc006993

#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */

#define CFG_LBLAWAR0_PRELIM 0x80000019 /* 64 MB window size */

#define CFG_MAX_FLASH_BANKS 1 /* number of banks */

#define CFG_MAX_FLASH_SECT 512 /* sectors per device */

/* local bus CS 1 */

#if 0

# define CFG_BR1_BASE 0xe9000000

# define CFG_LBLAWBAR1_PRELIM CFG_BR1_BASE

# define CFG_NAND_BASE CFG_BR1_BASE

# define CFG_LBLAWAR1_PRELIM CFG_LBLAWAR_DEFAULT

# define CFG_BR1_PRELIM CFG_BR1_BASE | CFG_BR_DEFAULT | BR_MS_UPMA

# define CFG_OR1_PRELIM CFG_OR_DEFAULT

#else

# define CFG_BR1_BASE 0xD0000000

# define CFG_NAND_BASE CFG_BR1_BASE

# define CFG_LBLAWBAR1_PRELIM CFG_BR1_BASE

# define CFG_LBLAWAR1_PRELIM 0x8000001b

#if 0

# define CFG_BR1_PRELIM ( CFG_BR1_BASE | (2<<BR_DECC_SHIFT) | BR_PS_8 | BR_MS_FCM | BR_V )

#endif

# define CFG_BR1_PRELIM ( CFG_BR1_BASE | (2<<BR_DECC_SHIFT) | BR_MS_FCM | BR_PS_8 | BR_V )

#endif

/* local bus CS 2 */

# define CFG_BR2_BASE 0xed000000

# define CFG_LBLAWBAR2_PRELIM CFG_BR2_BASE

# define CFG_OR2_PRELIM CFG_OR_DEFAULT

# define CFG_LBLAWAR2_PRELIM CFG_LBLAWAR_DEFAULT

#if defined(CONFIG_CPU_DAUGHTER_8313) || defined(CONFIG_TC1000_8313) || defined(CONFIG_SCRDB_8313) || defined(CONFIG_FRISER_8313) || defined(CONFIG_PTPIN) || defined(CONFIG_FIBER) || defined(CONFIG_LF7520) || defined(CONFIG_LF7550)|| defined(CONFIG_LF7511)

# define CFG_BR2_PRELIM CFG_BR2_BASE | CFG_BR_DEFAULT | BR_MS_UPMB

# define CFG_S8313_UPMB 1

#else

#define CFG_BR2_PRELIM CFG_BR2_BASE | CFG_BR_DEFAULT | BR_MS_UPMA

#endif

/* local bus CS 3 */

#if defined(CONFIG_SM2000_PTP_OUT)

#define CFG_BR3_BASE 0xec000000

#define CFG_LBLAWBAR3_PRELIM CFG_BR3_BASE

#define CFG_OR3_PRELIM CFG_OR_DEFAULT

#define CFG_LBLAWAR3_PRELIM CFG_LBLAWAR_DEFAULT

#define CFG_BR3_PRELIM CFG_BR3_BASE | CFG_BR_DEFAULT | BR_MS_UPMA

#else

# define CFG_BR3_BASE 0xfe000000

# define CFG_LBLAWBAR3_PRELIM CFG_BR3_BASE

# define CFG_LBLAWAR3_PRELIM CFG_LBLAWAR_DEFAULT

# define CFG_BR3_PRELIM CFG_BR3_BASE | CFG_BR_DEFAULT | BR_MS_UPMA

# define CFG_OR3_PRELIM CFG_OR_DEFAULT

#endif

#if 0 /*if close follow code the serial no printf why? ll to do*/

/* local bus CS 4 */

# define CFG_BR4_BASE 0xec000000

# define CFG_LBLAWBAR4_PRELIM CFG_BR4_BASE

# define CFG_LBLAWAR4_PRELIM CFG_LBLAWAR_DEFAULT

# define CFG_BR4_PRELIM CFG_BR4_BASE | CFG_BR_DEFAULT | BR_MS_UPMA

# define CFG_OR4_PRELIM CFG_OR_DEFAULT

#endif

#endif /* NAND_SPL */

/*

* NAND Boot Configuration

*/

# define CFG_MAX_NAND_DEVICE 1

# define NAND_MAX_CHIPS 1

# define CONFIG_MTD_NAND_VERIFY_WRITE

# define CFG_NAND_BOOT_QUIET

# undef CFG_NAND_BOOT_QUIET

/*

* 1) This must match u-boot-nand.lds

*

* #ifdef CONFIG_NAND_SPL

* use CFG_NAND_BASE as relocation address

* #else

* use CFG_MONITOR_BASE as relocation address ( usually TEXT )

*

*/

#define CFG_NAND_RELOC (0x4000)

#define CFG_NAND_PAGE_SIZE (2048)

#define CFG_NAND_BLOCK_SIZE (CFG_NAND_PAGE_SIZE*64)

#define CFG_NAND_FMR ((12 << FMR_CWTO_SHIFT) | (1 << FMR_AL_SHIFT) | FMR_ECCM )

#define CFG_NAND_BAD_BLOCK_POS (0)

#define CFG_NAND_U_BOOT_SIZE (384 << 10)

/* put it into top 1 mb */

#define CFG_NAND_U_BOOT_DST TEXT_BASE

#define CFG_NAND_U_BOOT_START (CFG_NAND_U_BOOT_DST + 0x120)

/* This must be undefined for CFG_RESET_ADDRESS to work */

#undef MPC83xx_RESET

#define CFG_RESET_ADDRESS CFG_NAND_U_BOOT_START

/*

* pass open firmware flat tree

*/

#define CONFIG_OF_FLAT_TREE 1

#define CONFIG_OF_BOARD_SETUP 1

#define OF_FLAT_TREE_MAX_SIZE 8192

#define OF_CPU "PowerPC,8313@0"

#define OF_SOC "soc8313@e0000000"

#define OF_TBCLK (bd->bi_busfreq / 4)

#define OF_STDOUT_PATH "/soc8313@e0000000/serial@4500"

/*

* Serial Port

*/

#define CONFIG_CONS_INDEX 1

#undef CONFIG_SERIAL_SOFTWARE_FIFO

#define CFG_NS16550

#define CFG_NS16550_SERIAL

#define CFG_NS16550_REG_SIZE 1

#define CFG_NS16550_CLK get_bus_freq(0)

#define CFG_BAUDRATE_TABLE \

{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}

#define CFG_NS16550_COM1 (CFG_IMMR+0x4500)

#define CFG_NS16550_COM2 (CFG_IMMR+0x4600)

#define CONFIG_CMDLINE_EDITING 1 /* add command line history modify by ll 20210406*/

/*

* I2C

*/

#undef CONFIG_HARD_I2C

#undef CONFIG_SOFT_I2C

#define CONFIG_FSL_I2C

#define CONFIG_I2C_MULTI_BUS

#define CONFIG_I2C_CMD_TREE

#define CFG_I2C_SPEED 400000

#define CFG_I2C_SLAVE 0x7F

#define CFG_I2C_NOPROBES {0x69}

#define CFG_I2C_OFFSET 0x3000

#define CFG_I2C2_OFFSET 0x3100

/*

* defined for SGMII config lsk 2018-4-8

*/

#define CONFIG_MPC8313_SGMII 1

/* TSEC */

#define CFG_TSEC1_OFFSET 0x24000

#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET)

#define CFG_TSEC2_OFFSET 0x25000

#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET)

/*

* TSEC configuration

*/

#define CONFIG_TSEC_ENET

#if defined(CONFIG_TSEC_ENET)

#if defined(CONFIG_SM2000_PTP_OUT)

# define CONFIG_MPC83XX_TSEC2 1

# define CONFIG_MPC83XX_TSEC2_NAME "TSEC2"

#elif defined(CONFIG_SM2000_NTP_OUT)

# define CONFIG_MPC83XX_TSEC2 1

# define CONFIG_MPC83XX_TSEC2_NAME "TSEC2"

#else

# define CONFIG_MPC83XX_TSEC1 1

# define CONFIG_MPC83XX_TSEC1_NAME "TSEC1"

# define CONFIG_MPC83XX_TSEC2 1

# define CONFIG_MPC83XX_TSEC2_NAME "TSEC2"

#endif

#if defined(CONFIG_SM1000)

#define TSEC1_PHY_ADDR 3

#define TSEC2_PHY_ADDR 0

#elif defined(CONFIG_SM2000_CC)

#define TSEC1_PHY_ADDR 0

#define TSEC2_PHY_ADDR 1

#elif defined(CONFIG_SM2000_PTP_OUT) || defined(CONFIG_SM2000_NTP_OUT)

#define TSEC2_PHY_ADDR 2

#elif defined(CONFIG_SM2000_NTP_OUT)

#define TSEC2_PHY_ADDR 2

#elif defined(CONFIG_MOC700)

#define TSEC1_PHY_ADDR 0

#define TSEC2_PHY_ADDR 1

#elif defined(CONFIG_LF7560)

#define TSEC1_PHY_ADDR 2

#define TSEC2_PHY_ADDR 3

#elif defined(CONFIG_LF7500)

#define TSEC1_PHY_ADDR 2

#define TSEC2_PHY_ADDR 3

#elif defined(CONFIG_LF7520)

#define TSEC1_PHY_ADDR 0

#define TSEC2_PHY_ADDR 1

#elif defined(CONFIG_LF7550)

#define TSEC1_PHY_ADDR 0

#define TSEC2_PHY_ADDR 1

#elif defined(CONFIG_LF7511)

#define TSEC1_PHY_ADDR 0

#define TSEC2_PHY_ADDR 1

#else

#define TSEC1_PHY_ADDR 0

#define TSEC2_PHY_ADDR 1

#endif

# define TSEC1_PHYIDX 0

# define TSEC2_PHYIDX 0

#endif /* CONFIG_TSEC_ENET */

/*

* Environment

*/

#if 0

#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */

#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x2000)

#define CFG_ENV_SIZE 0x2000

#endif

#if defined(CONFIG_NAND_U_BOOT)

#define CFG_ENV_IS_IN_NAND1

#define CFG_ENV_SIZECFG_NAND_BLOCK_SIZE

#define CFG_ENV_OFFSET((512<<10) - (CFG_NAND_BLOCK_SIZE<<1))

#elif !defined(CFG_RAMBOOT)

#define CFG_ENV_IS_IN_FLASH1

#define CFG_ENV_ADDR(CFG_MONITOR_BASE + 0x50000)

#define CFG_ENV_SECT_SIZE0x20000/* 128K(one sector) for env */

#define CFG_ENV_SIZE0x20000

/* Address and size of Redundant Environment Sector */

#else

#define CFG_ENV_IS_NOWHERE1/* Store ENV in memory only */

#define CFG_ENV_ADDR(CFG_MONITOR_BASE - 0x2000)

#define CFG_ENV_SIZE0x2000

#endif

#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */

#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */

#define CFG_BASE_COMMANDS ( CONFIG_CMD_DFL \

| CFG_CMD_PING\

| CFG_CMD_NET \

| CFG_CMD_MII\

| CFG_CMD_BOOTM \

| CFG_CMD_PCI \

| CFG_CMD_JFFS2 \

| CFG_CMD_NAND \

| ADD_FLASH_CMD \

| CFG_CMD_FLASH\

)

#if 0

#define CFG_RAMBOOT_COMMANDS ( CFG_BASE_COMMANDS & ~( CFG_CMD_ENV | CFG_CMD_LOADS | CFG_CMD_FLASH | CFG_CMD_IMLS))

#endif

#define CFG_RAMBOOT_COMMANDS ( CFG_BASE_COMMANDS & ~( CFG_CMD_ENV | CFG_CMD_LOADS | CFG_CMD_IMLS))

#define CONFIG_COMMANDS ( CFG_RAMBOOT_COMMANDS )

#include <cmd_confdefs.h>

/*

* WATCHDOG MADDNESS

*/

/*

* watchdog is not implemented for MPC83xx even though

* bits and pieces are present.

*

* Routine 'watchdog_reset' must be defined in BSP

*/

#undef CONFIG_WATCHDOG

/*

* HW watchdog is not implemented for MPC83xx even

* though bits and pieces are present.

*

* Routine 'hw_watchdog_reset' must be defined in BSP

*/

#undef CONFIG_HW_WATCHDOG

/*

* This is used by s8313.c and by the u-boot code

*

*/

#define CFG_WATCHDOG_VALUE 0xFFFFFFC3

/*

* Miscellaneous configurable options

*/

#define CFG_LONGHELP

#define CFG_PROMPT "=> "

/* Use the HUSH parser */

#define CFG_HUSH_PARSER

#ifdef CFG_HUSH_PARSER

# define CFG_PROMPT_HUSH_PS2 "=> "

#endif

/* console buffer size */

#define CFG_CBSIZE 1024

#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */

#define CFG_MAXARGS 16 /* max number of command args */

#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */

#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */

/*

* For booting Linux, the board info and command line data

* have to be in the first 8 MB of memory, since this is

* the maximum mapped by the Linux kernel during initialization.

*

* well not exactly ... values up to 254>>20 work...

*

*/

#define CFG_BOOTMAPSZ (254<<20)

/* Cache Configuration */

#define CFG_DCACHE_SIZE 16384

#define CFG_CACHELINE_SIZE 32

#if (CONFIG_COMMANDS & CFG_CMD_KGDB)

# define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/

#endif

#define CFG_RCWH_PCIHOST 0x80000000

#define ADD_HRCW_DEVICE ( \

HRCWH_BOOTSEQ_DISABLE |\

HRCWH_FROM_0X00000100 |\

HRCWH_ROM_LOC_NAND_LP_16BIT |\

HRCWH_RL_EXT_LEGACY |\

0)

#define ADD_HRCW_NET ( \

HRCWH_TSEC1M_IN_SGMII |\

HRCWH_TSEC2M_IN_SGMII | \

0)

#define CFG_HRCW_HIGH ( \

ADD_HRCW_DEVICE | \

ADD_HRCW_NET | \

HRCWH_PCI_HOST | \

HRCWH_PCI1_ARBITER_ENABLE |\

HRCWH_CORE_ENABLE |\

HRCWH_SW_WATCHDOG_DISABLE |\

HRCWH_BIG_ENDIAN |\

HRCWH_LALE_NORMAL |\

0)

/*

* 33MHz IN, 166MHz CSB, 333 DDR, 333 CORE

*/

#define CFG_HRCW_LOW (\

HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\

HRCWL_INIT |\

HRCWL_DDR_TO_SCB_CLK_2X1 |\

HRCWL_CSB_TO_CLKIN_5X1 |\

HRCWL_CORE_TO_CSB_2X1 |\

0)

/*

* System IO Config

*/

//#define CFG_SICRH (0x0) /* 3.3v @ 40 ohms */

#define CFG_SICRH (1<<(31-7)) /* use TSEC clock, 3.3v @ 40 ohms */

//#define CFG_SICRL (0x30000000)

#define CFG_SICRL (0x33FC0000) //// enable GPIO 28 29 30 31

#define CFG_HID0_INIT 0x000000000

#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK

#define CFG_HID2 HID2_HBE

/*

* DDR @ 0x00000000

*/

#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)

#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)

/*

* PCI @ 0x80000000

*/

#define CONFIG_PCI

/*

* General PCI

* Addresses are mapped 1-1.

*/

#ifdef CONFIG_PCI

# define CONFIG_PCI_PNP

# undef CONFIG_PCI_SCAN_SHOW

# define CFG_PCI_SUBSYS_VENDORID 0x1057

# define CFG_PCI1_MEM_BASE0x80000000

# define CFG_PCI1_MEM_PHYSCFG_PCI1_MEM_BASE

# define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */

# define CFG_PCI1_MMIO_BASE0x90000000

# define CFG_PCI1_MMIO_PHYSCFG_PCI1_MMIO_BASE

# define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */

#define CFG_PCI1_IO_BASE0x00000000

#define CFG_PCI1_IO_PHYS0xE2000000

#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */

# define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)

# define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)

# define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)

# define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)

# if defined(CONFIG_SCRDB_8313) || defined(CONFIG_ORION_8313) || defined(CONFIG_SCIMC) || defined(CONFIG_FRISER_8313) || defined(CONFIG_PTPIN) || defined(CONFIG_FIBER) ||defined(CONFIG_LF7520) || defined(CONFIG_LF7550)|| defined(CONFIG_LF7511)

# define CONFIG_NATSEMI

# undef NATSEMI_DEBUG

# endif

# ifndef CONFIG_PCI_PNP

# define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */

# define PCI_ENET0_IOADDR 0x80000000

# define PCI_ENET0_MEMADDR 0x80000000

# endif

#else

# define CFG_IBAT1L (0)

# define CFG_IBAT1U (0)

# define CFG_IBAT2L (0)

# define CFG_IBAT2U (0)

#endif

/*

* PCI2 not supported on 8313

*/

#if 1

#define CFG_IBAT3L (0xE8000000 | BATL_PP_10 | BATL_MEMCOHERENCE)

/*#define CFG_IBAT4L (0xD0000000 | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)*/

#define CFG_IBAT3U (0xE8000000 | BATU_BL_64M | BATU_VS | BATU_VP)

#define CFG_IBAT4L (0xD0000000 | BATL_PP_10 | BATL_MEMCOHERENCE)

/*#define CFG_IBAT4L (0xD0000000 | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)*/

#define CFG_IBAT4U (0xD0000000 | BATU_BL_256M | BATU_VS | BATU_VP)

#else

/*modify byll 20210401*/

#define CFG_IBAT3L (0)

#define CFG_IBAT3U (0)

#define CFG_IBAT4L (0)

#define CFG_IBAT4U (0)

#endif

/*

* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000

*/

#define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)

#define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)

/*

* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000

MODIFY BY LL 20210331

*/

#define CFG_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE)

#define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)

#define CFG_IBAT7L (0)

#define CFG_IBAT7U (0)

#define CFG_DBAT0L CFG_IBAT0L

#define CFG_DBAT0U CFG_IBAT0U

#define CFG_DBAT1L CFG_IBAT1L

#define CFG_DBAT1U CFG_IBAT1U

#define CFG_DBAT2L CFG_IBAT2L

#define CFG_DBAT2U CFG_IBAT2U

#define CFG_DBAT3L CFG_IBAT3L

#define CFG_DBAT3U CFG_IBAT3U

#define CFG_DBAT4L CFG_IBAT4L

#define CFG_DBAT4U CFG_IBAT4U

#define CFG_DBAT5L CFG_IBAT5L

#define CFG_DBAT5U CFG_IBAT5U

#define CFG_DBAT6L CFG_IBAT6L

#define CFG_DBAT6U CFG_IBAT6U

#define CFG_DBAT7L CFG_IBAT7L

#define CFG_DBAT7U CFG_IBAT7U

/*

* Internal Definitions

*

* Boot Flags

*/

#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */

#define BOOTFLAG_WARM 0x02 /* Software reboot */

#define UBOOT_BAUDRATE 115200

#if (CONFIG_COMMANDS & CFG_CMD_KGDB)

# define CONFIG_KGDB_BAUDRATE UBOOT_BAUDRATE /* speed of kgdb serial port */

# define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */

#endif

/*

* Environment Configuration

*/

#undef CONFIG_VERSION_VARIABLE

#define CONFIG_ENV_OVERWRITE

#define CONFIG_NET_MULTI

#define CONFIG_BOOTFILE uImage

#define CONFIG_SERVERIP 192.168.1.123 /*81.128*/

#undef CONFIG_SHOW_BOOT_PROGRESS

#define CFG_LOAD_ADDR 100000

#define CONFIG_LOADADDR CFG_LOAD_ADDR

#define CONFIG_AUTOBOOT_KEYED

#define CONFIG_AUTOBOOT_PROMPT "Boot in %d seconds\n"

#define CONFIG_AUTOBOOT_DELAY_STR "."

#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */

#define CONFIG_BAUDRATEUBOOT_BAUDRATE

/*

* JFFS2 configuration + mtdparts

*/

#define CONFIG_JFFS2_NAND

#define CONFIG_JFFS2_DEV "nand0"

#define CONFIG_JFFS2_CMDLINE

# if 1

/* should be the same for all of our 8313 designs */

#define MTDIDS_DEFAULT "nand0=s8313.nand"

#define MTDPARTS_DEFAULT "mtdparts=mtdparts=s8313.nand:" \

"128k(stage0)," \

"896k(boot)," \

"1m(factory)," \

"1m(control)"

/* may vary depending on amount of NAND or other considerations */

#define CONFIG_MTDPARTS MTDPARTS_DEFAULT \

"," \

"16m(os.1)," \

"8m(uImage.1)," \

"16m(os.2)," \

"8m(uImage.2)," \

"76m(appl.1)," \

"76m(appl.2)," \

"8m(config.1)," \

"8m(config.2)," \

"-(pst)" \

"\0"

#else

#define MTDIDS_DEFAULT "nor0=s8313.flash,nand0=s8313.nand"

#define MTDPARTS_DEFAULT "mtdparts=mtdparts=s8313.flash:" \

"2m(uboot),"\

"s8313.nand:128k(stage0)," \

"896k(boot)," \

"1m(factory)," \

"1m(control)" \

"16m(os.1)," \

"8m(uImage.1)," \

"16m(os.2)," \

"8m(uImage.2)," \

"76m(appl.1)," \

"76m(appl.2)," \

"8m(config.1)," \

"8m(config.2)," \

"30m(pst)" \

/* may vary depending on amount of NAND or other considerations */

#define CONFIG_MTDPARTS MTDPARTS_DEFAULT \

"\0"

#endif

#define NAND_CACHE_PAGES 4

/*

* Manufacturing/devlopment scripts to write to NAND flash

*/

#define CONFIG_HAS_ETH1

# define CONFIG_TARGET "LF7511"

# define CONFIG_ETHPRIME "TSEC1"

# define CONFIG_HOSTNAME "LF7511"

# define CONFIG_IPADDR 192.168.1.113 /*81.113*/

# define CONFIG_ETHADDR 78:CA:83:BF:05:6A

# define CONFIG_ETH1ADDR 78:CA:83:BF:05:6B

#define CONFIG_NEW_STAGE0 "wstage0=" \

"tftp $loadaddr ${target}/u-boot-spl.bin && " \

"nand erase stage0 && " \

"nand write.jffs2 $fileaddr stage0 $filesize" \

"\0"

#define CONFIG_NEW_BOOT "wboot=" \

"tftp $loadaddr ${target}/u-boot.bin && " \

"nand erase boot && " \

"nand write.jffs2 $fileaddr boot $filesize" \

"\0"

/*

* force the size to 0x800000 since the write has to be

* on a and 0x800000 is larger than we can currently

* build to...

*/

#define CONFIG_NEW_UIMAGE "wuimage=" \

"tftp $loadaddr ${target}/uImage ; " \

"if test $? -gt 0 ; then " \

"test 1=2 ; " \

"else " \

"nand erase uImage.1 ; " \

"nand erase uImage.2 ; " \

"nand write $fileaddr uImage.1 800000 ; " \

"nand write $fileaddr uImage.2 800000 ; " \

"fi" \

"\0"

#define CONFIG_NEW_OS "wos=" \

"tftp $loadaddr ${target}/os.jffs2 && " \

"nand erase os.1 && " \

"nand erase os.2 && " \

"nand write.jffs2 $fileaddr os.1 $filesize && " \

"nand write.jffs2 $fileaddr os.2 $filesize && " \

"run wuimage " \

"\0"

#define CONFIG_NEW_CONTROL "wcontrol=" \

"tftp $loadaddr ${target}/control.jffs2 && " \

"nand erase control && " \

"nand write.jffs2 $fileaddr control $filesize" \

"\0"

#define CONFIG_NEW_FACTORY "wfactory=" \

"tftp $loadaddr ${target}/factory.jffs2 && " \

"nand erase factory && " \

"nand write.jffs2 $fileaddr factory $filesize" \

"\0"

/*

* do not write uImage here --- wait until everything

* else is writtent so if it fails there will be enough

* left over to fix the problem in linux

*/

#define CONFIG_NEW_OSS "woss=" \

"run wstage0 && " \

"run wboot && " \

"run wos && " \

"run wcontrol" \

"\0"

#define CONFIG_NEW_APPL "wappl=" \

"tftp $loadaddr ${target}/appl.jffs2 && " \

"nand erase appl.1 && " \

"nand write.jffs2 $fileaddr appl.1 $filesize && " \

"nand erase appl.2 && " \

"nand write.jffs2 $fileaddr appl.2 $filesize" \

"\0"

#define CONFIG_NEW_CONFIG "wconfig=" \

"tftp $loadaddr ${target}/config.jffs2 && " \

"nand erase config.1 && " \

"nand write.jffs2 $fileaddr config.1 $filesize && " \

"nand erase config.2 && " \

"nand write.jffs2 $fileaddr config.2 $filesize" \

"\0"

#define CONFIG_NEW_PST "wpst=" \

"tftp $loadaddr ${target}/pst.jffs2 && " \

"nand erase pst && " \

"nand write.jffs2 $fileaddr pst $filesize" \

"\0"

#define CONFIG_NEW_MOST "wmost=" \

"run woss && " \

"run wappl && " \

"run wconfig && " \

"run wpst " \

"\0"

#define CONFIG_NEW_ALL "wall=" \

"run wmost && " \

"run wfactory ; " \

"if test $? -gt 0 ; then " \

"echo ERROR: UNABLE TO COMPLETE SOFTWARE LOAD ; " \

"else " \

"echo INFO: SOFTWARE LOAD COMPLETE ; " \

"fi" \

"\0"

/*

* Manufacturing/devlopment scripts to boot partitions

*/

#define CONFIG_BA_R "bar=" \

"symwdt ; " \

"setenv bootargs " \

"root=/dev/ram rw " \

"rdinit=$start " \

"console=ttyS0,$baudrate " \

"${mtdparts} " \

"next=$next " \

"bprog=$bprog " \

"last=$last " \

"target=$target " \

"wdt=$wdt " \

"bver=$bver" \

"\0"

#define CONFIG_BT_T "boot.t=" \

"chpart control ; " \

"symscrl next.scr ; " \

"symscrl last.scr ; " \

"symlft ; " \

"tftp $daddr ${target}/dtb && " \

"tftp $kaddr ${target}/$bootfile && " \

"run bar ; " \

"bootm $kaddr - $daddr" \

"\0"

#if defined(CONFIG_FRISER_8313)

/* not load fpga */

#define CONFIG_BT_NX "boot.nx=" \

"chpart os.${next} ; " \

"fsload $daddr dtb ; " \

"if test $? -gt 0 ; then " \

"set bprog boot-dtb ; " \

"test 1=2 ; " \

"else " \

"run get.uImage && " \

"run bar && " \

"bootm $kaddr - $daddr ; " \

"if test $? -gt 0 ; then " \

"set bprog boot-fallback && " \

"run get.uImage.j && " \

"run bar && " \

"bootm $kaddr - $daddr ; " \

"fi ; " \

"\0"

#elif 1

/* fail of fpga load fails boot */

#define CONFIG_BT_NX "boot.nx=" \

"chpart os.${next} && " \

"symlfl ; " \

"if test $? -gt 0 ; then " \

"set bprog boot-fpga ; " \

"test 1=2 ; " \

"else " \

"fsload $daddr dtb ; " \

"if test $? -gt 0 ; then " \

"set bprog boot-dtb ; " \

"test 1=2 ; " \

"else " \

"run get.uImage && " \

"run bar && " \

"bootm $kaddr - $daddr ; " \

"if test $? -gt 0 ; then " \

"set bprog boot-fallback && " \

"run get.uImage.j && " \

"run bar && " \

"bootm $kaddr - $daddr ; " \

"fi ; " \

"\0"

#else

/* fail of fpga load - boot conintues */

#define CONFIG_BT_NX "boot.nx=" \

"chpart os.${next} ; " \

"symlfl ; " \

"if test $? -gt 0 ; then " \

"set bprog boot-fpga ; " \

"fi ; " \

"fsload $daddr dtb ; " \

"if test $? -gt 0 ; then " \

"set bprog boot-dtb ; " \

"fi ; " \

"run get.uImage && " \

"run bar && " \

"bootm $kaddr - $daddr ; " \

"if test $? -gt 0 ; then " \

"set bprog boot-fallback ; " \

"run get.uImage.j && " \

"run bar && " \

"bootm $kaddr - $daddr ; " \

"fi " \

"\0"

#endif

#define CONFIG_BT_1 "boot.1=" \

"set next 1 ; " \

"set bprog boot-ok-1 ; " \

"run boot.nx ; " \

"if test $? -gt 0 ; then " \

"set next 2 ; " \

"set bprog boot-swap-2 ; " \

"run boot.nx ; " \

"fi" \

"\0"

#define CONFIG_BT_2 "boot.2=" \

"set next 2 ; " \

"set bprog boot-ok-2 ; " \

"run boot.nx ; " \

"if test $? -gt 0 ; then " \

"set next 1 ; " \

"set bprog boot-swap-1 ; " \

"run boot.nx ; " \

"fi" \

"\0"

#define CONFIG_BT_N "boot.n=" \

"chpart control ; " \

"symscrl next.scr ; " \

"symscrl last.scr ; " \

"if test ${next} -eq 1 ; then " \

"run boot.1 ; " \

"else " \

"run boot.2 ; " \

"fi ; " \

"symblnk " \

"\0"

#define CONFIG_GET_UIMAGE "get.uImage=" \

"echo BOOT FROM UIMAGE ; symuimage $kaddr uImage.${next} 0" \

"\0"

#define CONFIG_GET_UIMAGE_J "get.uImage.j=" \

"echo BOOT FROM JFFS2 ; fsload $kaddr $bootfile" \

"\0"

#define XMK_STR(x) #x

#define MK_STR(x) XMK_STR(x)

/* "bver=\"" CONFIG_TARGET " (" __DATE__ " "__TIME__ ")\"\0" */

#if defined(CONFIG_SCRDB_8313)

#define SYMM_BUILD_NAME CONFIG_SCRDB_8313_BLD

#elif defined(CONFIG_FRISER_8313)

#define SYMM_BUILD_NAME CONFIG_FRISER_8313_BLD

#elif defined(CONFIG_ORION_8313)

#define SYMM_BUILD_NAME CONFIG_ORION_8313_BLD

#elif defined(CONFIG_SM1000)

#define SYMM_BUILD_NAME CONFIG_SM1000_BLD

#elif defined(CONFIG_SM2000_MC)

#define SYMM_BUILD_NAME CONFIG_SM2000_MC_BLD

#elif defined(CONFIG_SM2000_CC)

#define SYMM_BUILD_NAME CONFIG_SM2000_CC_BLD

#elif defined(CONFIG_LF7300)

#define SYMM_BUILD_NAME CONFIG_LF7300_BLD

#elif defined(CONFIG_LF7520)

#define SYMM_BUILD_NAME CONFIG_LF7520_BLD

#elif defined(CONFIG_LF7560)

#define SYMM_BUILD_NAME CONFIG_LF7560_BLD

#elif defined(CONFIG_LF7550)

#define SYMM_BUILD_NAME CONFIG_LF7550_BLD

#elif defined(CONFIG_LF7511)

#define SYMM_BUILD_NAME CONFIG_LF7511_BLD

#else

#define SYMM_BUILD_NAME CONFIG_SM2000_BLD

#endif

#define CONFIG_EXTRA_ENV_SETTINGS \

"target=" CONFIG_TARGET "\0" \

"ethprime=" CONFIG_ETHPRIME "\0" \

"kaddr=F000000\0" \

"daddr=FE00000\0" \

"start=linuxrc\0" \

"next=1\0" \

"bprog=undefined\0" \

"fpgaName=fpga\0" \

"bver=\"" SYMM_BUILD_NAME "\"\0" \

CONFIG_MTDPARTS \

CONFIG_GET_UIMAGE \

CONFIG_GET_UIMAGE_J \

CONFIG_NEW_STAGE0 \

CONFIG_NEW_BOOT \

CONFIG_NEW_OS \

CONFIG_NEW_UIMAGE \

CONFIG_NEW_FACTORY \

CONFIG_NEW_CONTROL \

CONFIG_NEW_OSS \

CONFIG_NEW_APPL \

CONFIG_NEW_CONFIG \

CONFIG_NEW_PST \

CONFIG_NEW_MOST \

CONFIG_NEW_ALL \

CONFIG_BA_R \

CONFIG_BT_T \

CONFIG_BT_NX \

CONFIG_BT_1 \

CONFIG_BT_2 \

CONFIG_BT_N \

"\0"

#define CONFIG_BOOTCOMMAND "run boot.n"

#endif /* __CONFIG_H */

yipingwang · ‎04-18-2021

Please specify TEXT_BASE as NOR FLASH start address 0xe8000000.

leilei987 · ‎04-18-2021

hi

yiping

I have tried to change my advice? ，But it didn't work

my private script:

ARCH = ppc
CPU = mpc83xx
BOARD = s8313
CONFIG_NAND_U_BOOT = y
CONFIG_NAND_LP = y

s8313? is? my private board name

it's base on mpc8313erdb config

I make sure I don't want the two bold lines of macro definition above

but modify to "n" the uboot.img size??It went from 325K to 275K，And tftp? not available

tftp
**bleep**: 0FFC1FD8 XER: 20000000 LR: 0FFC1258 REGS: 0ff10b58 TRAP: 0700 DAR: 0000B032
MSR: 0008b032 EE: 1 PR: 0 FP: 1 ME: 1 IR/DR: 11

GPR00: 0FFC1FD8 0FF10C48 00000080 00007949 0FF32CC8 00000001 00000000 00000000
GPR08: 00000004 00000000 0FFFD260 00000000 28022022 AB87FAF7 0FFF8000 0FFEEA5C
GPR16: 0FFF333C 00000000 00000000 00000000 00000000 00000000 00000000 0FF32CC8
GPR24: 0FF32C88 FFFFFFFF E0024000 0FFF89E0 0FF32CC8 0FF10F58 0FFF8790 0FFF40D8
Call backtrace:
0FFC1240 0FFC24D4 0FFBB76C 0FFBA094 0FFD0914 0FFD84D4 0FFD7B44
0FFD7CF4 0FFC8428 0FFB877C 0FFB46AC
Program Check Exception
resetting the board, address: 0ff00120

Reset Configuration Word High Register (RCWHR? ?BMS??Set 1 or 0
thanks

yipingwang · ‎04-19-2021

Please compile u-boot with configs/MPC8313ERDB_33_defconfig or MPC8313ERDB_66_defconfig.

Please modify your u-boot configuration based on include/configs/MPC8313ERDB.h.

leilei987 · ‎04-20-2021

hi

yiping

so good

This problem has been resolved 。

tank you very much!

best regards!

leilei987 · ‎04-19-2021

oh i can‘t stand it any more

because my uboot version is 1.1.6

there is no configs/MPC8313ERDB_33_defconfig or MPC8313ERDB_66_defconfig file

I took over the project in mid-stream，None of my colleagues knew much about it

in 1.1.6 version my private .h is based on include/configs/MPC8313ERDB.h

and i try download uboor code in qoriq sdk v1.9

but Machine type not have 8313erdb!

I'm at the end of my tether