iMX8mp standalone u-boot build (32 bit cross compiler)

[habib_farahani]

Hello,

Due to some legacy dependencies I need to be able to build uboot dor imx8 using gcc-12.2.1 (arm-none-linux-gnueabihf-) cross compiler.   I have retrived the u-boot code from BSP 6.6.23 and when I try to build the code I hit a snap with the arm8 assembler.  Would anyone know how I can circumvent this failure?

from arch/arm/cpu/armv8/cache_v8.c:10:
arch/arm/cpu/armv8/cache_v8.c: In function ‘get_effective_el’:
include/linux/bitops.h:11:38: warning: left shift count >= width of type [-Wshift-count-overflow]
11 | #define BIT(nr) (1UL << (nr))
| ^~
arch/arm/cpu/armv8/cache_v8.c:54:31: note: in expansion of macro ‘BIT’
54 | if (hcr_el2 & BIT(HCR_EL2_E2H_BIT))
| ^~~
arch/arm/cpu/armv8/cache_v8.c: In function ‘find_pte’:
arch/arm/cpu/armv8/cache_v8.c:159:23: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
159 | pte = (u64*)(*pte & 0x0000fffffffff000ULL);
| ^
arch/arm/cpu/armv8/cache_v8.c: In function ‘map_range’:
arch/arm/cpu/armv8/cache_v8.c:330:30: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
330 | next_table = (u64 *)(table[i] & GENMASK_ULL(47, PAGE_SHIFT));
| ^
In file included from arch/arm/cpu/armv8/cache_v8.c:17:
arch/arm/cpu/armv8/cache_v8.c: In function ‘mmu_setup’:
./arch/arm/include/asm/armv8/mmu.h:38:43: warning: left shift count >= width of type [-Wshift-count-overflow]
38 | (UL(0xff) << (MT_NORMAL * 8)))
| ^~
arch/arm/cpu/armv8/cache_v8.c:473:27: note: in expansion of macro ‘MEMORY_ATTRIBUTES’
473 | MEMORY_ATTRIBUTES);
| ^~~~~~~~~~~~~~~~~
arch/arm/cpu/armv8/cache_v8.c: In function ‘set_one_region’:
./arch/arm/include/asm/armv8/mmu.h:67:40: warning: left shift count >= width of type [-Wshift-count-overflow]
67 | #define PTE_BLOCK_PXN (UL(1) << 53)
| ^~
./arch/arm/include/asm/armv8/mmu.h:75:34: note: in expansion of macro ‘PTE_BLOCK_PXN’
75 | #define PMD_ATTRMASK (PTE_BLOCK_PXN | \
| ^~~~~~~~~~~~~
arch/arm/cpu/armv8/cache_v8.c:607:34: note: in expansion of macro ‘PMD_ATTRMASK’
607 | *pte &= ~PMD_ATTRMASK;
| ^~~~~~~~~~~~
./arch/arm/include/asm/armv8/mmu.h:68:40: warning: left shift count >= width of type [-Wshift-count-overflow]
68 | #define PTE_BLOCK_UXN (UL(1) << 54)
| ^~
./arch/arm/include/asm/armv8/mmu.h:76:34: note: in expansion of macro ‘PTE_BLOCK_UXN’
76 | PTE_BLOCK_UXN | \
| ^~~~~~~~~~~~~
arch/arm/cpu/armv8/cache_v8.c:607:34: note: in expansion of macro ‘PMD_ATTRMASK’
607 | *pte &= ~PMD_ATTRMASK;
| ^~~~~~~~~~~~
./arch/arm/include/asm/armv8/mmu.h:67:40: warning: left shift count >= width of type [-Wshift-count-overflow]
67 | #define PTE_BLOCK_PXN (UL(1) << 53)
| ^~
./arch/arm/include/asm/armv8/mmu.h:75:34: note: in expansion of macro ‘PTE_BLOCK_PXN’
75 | #define PMD_ATTRMASK (PTE_BLOCK_PXN | \
| ^~~~~~~~~~~~~
arch/arm/cpu/armv8/cache_v8.c:608:41: note: in expansion of macro ‘PMD_ATTRMASK’
608 | *pte |= attrs & PMD_ATTRMASK;
| ^~~~~~~~~~~~
./arch/arm/include/asm/armv8/mmu.h:68:40: warning: left shift count >= width of type [-Wshift-count-overflow]
68 | #define PTE_BLOCK_UXN (UL(1) << 54)
| ^~
./arch/arm/include/asm/armv8/mmu.h:76:34: note: in expansion of macro ‘PTE_BLOCK_UXN’
76 | PTE_BLOCK_UXN | \
| ^~~~~~~~~~~~~
arch/arm/cpu/armv8/cache_v8.c:608:41: note: in expansion of macro ‘PMD_ATTRMASK’
608 | *pte |= attrs & PMD_ATTRMASK;
| ^~~~~~~~~~~~
AS arch/arm/cpu/armv8/cache.o
cc1: warning: unknown register name: x18
./arch/arm/include/asm/macro.h: Assembler messages:
./arch/arm/include/asm/macro.h:65: Warning: unknown register 'x30' -- .req ignored
arch/arm/cpu/armv8/cache.S:27: Error: ARM register expected -- `lsl x12,x0,#1'
arch/arm/cpu/armv8/cache.S:28: Error: selected processor does not support requested special purpose register -- `msr csselr_el1,x12'
arch/arm/cpu/armv8/cache.S:30: Error: ARM register expected -- `mrs x6,ccsidr_el1'
arch/arm/cpu/armv8/cache.S:31: Error: ARM register expected -- `ubfx x2,x6,#0,#3'
arch/arm/cpu/armv8/cache.S:32: Error: ARM register expected -- `ubfx x3,x6,#3,#10'
arch/arm/cpu/armv8/cache.S:33: Error: ARM register expected -- `ubfx x4,x6,#13,#15'
arch/arm/cpu/armv8/cache.S:34: Error: ARM register expected -- `add x2,x2,#4'
arch/arm/cpu/armv8/cache.S:35: Error: ARM register expected -- `clz w5,w3'
arch/arm/cpu/armv8/cache.S:43: Error: ARM register expected -- `mov x6,x3'
arch/arm/cpu/armv8/cache.S:45: Error: ARM register expected -- `lsl x7,x6,x5'
arch/arm/cpu/armv8/cache.S:46: Error: ARM register expected -- `orr x9,x12,x7'
arch/arm/cpu/armv8/cache.S:47: Error: ARM register expected -- `lsl x7,x4,x2'
arch/arm/cpu/armv8/cache.S:48: Error: ARM register expected -- `orr x9,x9,x7'
arch/arm/cpu/armv8/cache.S:49: Error: bad instruction `tbz w1,#0,1f'
arch/arm/cpu/armv8/cache.S:50: Error: bad instruction `dc isw,x9'

[Chavira]

Hi @habib_farahani!

Thank you for contacting NXP Support!

Unfortunately that is not possible, it is needed the aarch64-linux-gnu compiler.

Please consult the chapter 10.6.2.3 of this guide.

Best Regards!

Chavira

[habib_farahani]

Hi,

Thanks for confirmation.  What Kernel?  Can I build it using a 32 Cross Compiler?