The Power architecture has never had a divide-by-zero exception. If you want one then the compiler has to generate code to check the divisor before performing the division. Possibly with "twequi".
> If I expect to have exception for dividing by 0, what should I configure to
> enable this exception?
If the CPU has floating point hardware, then there's an enable for a floating point divide-by-zero exception, but you're wanting the integer one to trap.
> or what kind of compiling option should be used to guarantee this exception?
Depends on the compiler. Read all the documentaiton on it, or ask in a forum specific to that compiler.
Of course you should have asked Google, which for "ppc divide zero trap gcc" finds:
http://fixunix.com/embedded/341544-divide-zero-does-not-crash.html
The behavior of integer division by 0 is undefined per the C Languagestandard and, hence, implementation-dependent. On x86, division by 0produces a hardware exception. On x86 linux, this exception is presentedto the program as a signal. However, a conforming implementation maychoose to do anything else that is convenient: nothing (leave quotientunmodified), produce random value for the quotient, kill the process.
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Yes, that's a property of the PowerPC archictecture. AFAIK the theory
of the hardware designers was that the compiler should produce code
equivalent to:
q=n/d;
if (d == 0)
raise(SIGFPE);
The idea is that the check would be performed during the latency of
the division, so it would usually not cost extra time. So one could
make the hardware simpler by not putting in the check there. I may be
confusing PowerPC with another RISC architecture (most likely MIPS)
wrt this aspect, though.
If you want to have divide-by-zeros trap in conforming C code, then you have to add tests on the divisor, or call a function to perform all divides and have it check, or use C++ and overload the "/" operator.
Tom
