UJA1169AXF: Why does CW sometimes wait for the third wake-up frame instead of the second?

[Zhaohguanyu]

Hi NXP Team, We have two batches of boards that use the same UJA1169AXF and identical firmware, but they show different CW-flag timing after CAN wake-up: Event

Board-A sequence Board-B sequence Board A When the second wake-up frame is sent, V1 rises to 5 V, yet the CW flag in register 0x63 remains 0. Only after the third wake-up frame does CW become 1.

Board B With the second wake-up frame, V1 rises to 5 V and CW is already set to 1; no third frame is needed.

Could you explain what on-board parameter makes the CW bit wait for an extra frame on some boards? Is it related to V1 rise time, PNP load current, or another analog threshold that gates the internal “wake-up confirmed” signal?

Thanks for any hints!

Best regards, Zhaoguanyu

[JozefKozon]

Hello Zhao,

are you using one or more of our UJA1169Ax-EVBs? If yes, please state which you are using. 

If you are using your own design, please share your schematic with voltage levels and part values. 

With Best Regards,

Jozef

[Zhaohguanyu]

Thank you for your reply. We are indeed using our own design, but unfortunately, I am unable to share the schematic diagram
Has there been a similar case before? If so, please provide some directions for investigation

[JozefKozon]

Hello Zhao,

I have checked older cases, but couldn't find any other customer reporting similar CW flag issue.

Likely causes for the third wake-up frame requirement:

• Slower V1 rise time due to:
  • Larger load on V1 (microcontroller + peripherals).
  • External PNP transistor response.
  • Higher ESR or smaller output capacitor.
• Threshold configuration differences (MTPNV settings for V1 undervoltage or reset length).
• Startup timing: CW is latched only after reset completes and CAN transceiver is ready.

Please check following:

• Compare V1 ramp profiles on both boards (oscilloscope).
• Check PNP transistor type and shunt resistor value (UJA1169A only).
• Verify MTPNV settings for V1 undervoltage threshold and reset length.
• Confirm output capacitor ESR and placement.

With Best Regards,

Jozef

[Zhaohguanyu]

Hello Jozef

Firstly, please help to take a look at the waveform of V1,
I need to confirm with the hardware engineer regarding the rest

2 frames V1 ：

3 frames V1：

Also, may I ask what impact the slope of V1 will have

With Best Regards,

Zhao

[JozefKozon]

Hello Zhao,

These slopes are relatively slow compared to typical CAN dominant/recessive transitions.
Effect:

• A slow slope increases the time V1 spends in the threshold region, which can cause:
  • Uncertain dominant detection (device waits longer to confirm a valid dominant state).
  • Possible failure of wake-up frame validation, especially if the frame timing is tight.
• If the slope is too shallow, the internal filter may classify the edge as noise or incomplete, forcing the device to wait for another frame.

With Best Regards,

Jozef

[Zhaohguanyu]

Hello Jozef,

In my waveform diagram, 2 frames can set the CW of SBC, and the rise time of V1 is 248us,
Three frames can set the CW of SBC (which I think is problematic), and the rise time of V1 is 195us,
On the contrary, slower is normal
It seems to be the opposite of what you said

Also, in the case of 2 frames, is it related that the voltage of V1 during sleep is not 0V

With Best Regards,

Zhao

[JozefKozon]

Hello Zhao,

I need to contact an application engineer for advice. The application engineers always require following information. Please share them. Also please share the schematic if possible.

Customer: ?

End Customer: ?

End Application: ?

Country: China

Annual Volume: ?

With Best Regards,

Jozef