I have met some questions about UJA1135 SBC’ SPI communication.
1. When I tried to control MCU to read the contents of any selected register in SBC by SPI, the data returned was always 0.
2. I want to configurate the LIMP pin into outputting the low level and the HVIO4 pin into the high level, so I write 0x02(address), 0x04(data) and 0x33(address),0x0D(data). And I know the LSB of the address should be 0 to indicate a write operation. However, these operations failed.
I wonder if there are someplace that I neglected or I did something wrong.
Do you have a logic analyzer or an oscilloscope to check if the timing and format of the SPI message is correct?
Please note that the UJA1135 uses the “Mode 1” SPI protocol, which means that an inactive state of clock signal is low (CPOL = 0) and data are captured on the falling edge of clock signal and changed on the rising edge (CPHA = 1):
Also note that the 7-bit register address needs to be placed in the upper 7 bits of the first byte and the Read/Write bit is in the LSB:
For example, the 7-bit address of the Fail-safe control register (0x02) translates to 0x04 (0x02 << 1) for a write and 0x05 ([0x02 << 1] | 0x01) for a read.
I hope it helps.
Thanks for your reply. But I found the reason of my problem should be another one. That the factory preset values had been restored caused the SBC entered Forced Normal Mode. So the SPI communication was limited in the Forced Normal Mode.
Now I hope to exit the Forced Normal Mode and let SBC work in the normal mode, so I followed the data sheet. First, pin RSTN and pin CANL are pulled down to GND, and pin CANH is pulled up to 12V. After the factory preset values have been restored, I download the program with MTPNV to MCU(I want to disable the bit FNMC) while the SBC not power-off. Next I make MCU and SBC power-off and then MCU power-on. Finally I read bit FNMC and some other bits find that SBC is still in Forced Normal Mode.
I wonder what's wrong with my methods and a new SBC works in normal mode or forced normal mode.