TEF8102 Cascade Chirp Control problem

[jack_huang1]

Dears：

         The product uses NXP TEF8102 program 5 pieces of cascade, after FPGA processing, the data is transferred to NXP S32R294 for transmission. Currently, when debugging TEF8102 cascade, it is found that the trigger pin control cannot be used. The specific information is as follows:

          Below are instructions for configuring the trigger pin：

           jack_huang1_0-1672620709101.png

          The register description is detailed below：jack_huang1_1-1672620788784.png

bit 1 display is not USED. How should I configure this register? Thanks!

[guoweisun]

Please submit ticket for this part question.

Home (nxp.com)

[jack_huang1]

Dear guoweisun:

         I have submitted it on the CASE, CAS number: 00510005, thank you!